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PDF TSC80C31 Data sheet ( Hoja de datos )
| Número de pieza | TSC80C31 | |
| Descripción | (TSC80C31 / TSC80C51) CMOS 0 to 44 MHz Single-Chip 8 Bit Microcontroller | |
| Fabricantes | TEMIC Semiconductors | |
| Logotipo |  |
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TSC80C31/80C51
CMOS 0 to 44 MHz Single-Chip 8 Bit Microcontroller
Description
The TSC80C31/80C51 is high performance SCMOS
versions of the 8051 NMOS single chip 8 bit µC.
The fully static design of the TSC80C31/80C51 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TSC80C31/80C51 retains all the features of the 8051
: 4 K bytes of ROM ; 128 bytes of RAM ; 32 I/O lines ;
two 16 bit timers ; a 5-source, 2-level interrupt structure
; a full duplex serial port ; and on-chip oscillator and clock
circuits.
In addition, the TSC80C31/80C51 has two
software-selectable modes of reduced activity for further
reduction in power consumption. In the Idle Mode the
CPU is frozen while the RAM, the timers, the serial port,
and the interrupt system continue to function. In the
Power Down Mode the RAM is saved and all other
functions are inoperative.
The TSC80C31/80C51 is manufactured using SCMOS
process which allows them to run from 0 up to 44 MHz
with VCC = 5 V. The TSC80C31/80C51 is also available
at 20 MHz with 2.7 V < Vcc < 5.5 V.
D TSC80C31/80C51-L16 : Low power version
Vcc : 2.7–5.5 V Freq : 0–16 MHz
D TSC80C31/80C51-L20 : Low power version
Vcc : 2.7–5.5 V Freq : 0–20 MHz
D TSC80C31/80C51-12 : 0 to 12 MHz
D TSC80C31/80C51-20 : 0 to 20 MHz
D TSC80C31/80C51-25 : 0 to 25 MHz
D TSC80C31/80C51-30 : 0 to 30 MHz
D TSC80C31/80C51-36 : 0 to 36 MHz
D TSC80C31/80C51-40 : 0 to 40 MHz
D TSC80C31/80C51-44 : 0 to 44 MHz*
* Commercial and Industrial temperature range only. For other speed
and range please consult your sale office.
Features
D Power control modes
D 128 bytes of RAM
D 4 K bytes of ROM (TSC80C31/80C51)
D 32 programmable I/O lines
D Two 16 bit timer/counter
D 64 K program memory space
D 64 K data memory space
D Fully static design
D 0.8 µm CMOS process
D Boolean processor
D 5 interrupt sources
D Programmable serial port
D Temperature range : commercial, industrial, automotive and
military
Optional
D Secret ROM : Encryption
D Secret TAG : Identification number
MATRA MHS
Rev. E (14 Jan.97)
www.DataSheet.in
1
1 page  
TSC80C31/80C51
PSEN
XTAL1
Program Store Enable output is the read strobe to external
Program Memory. PSEN is activated twice each machine
cycle during fetches from external Program Memory.
(However, when executing out of external Program
Memory, two activations of PSEN are skipped during
each access to external Data Memory). PSEN is not
activated during fetches from internal Program Memory.
PSEN can sink or source 8 LS TTL inputs. It can drive
CMOS inputs without an external pullup.
Input to the inverting amplifier that forms the oscillator.
Receives the external oscillator signal when an external
oscillator is used.
XTAL2
Output of the inverting amplifier that forms the oscillator.
This pin should be floated when an external oscillator is
used.
EA
When EA is held high, the CPU executes out of internal
Program Memory (unless the Program Counter exceeds
3 FFFH). When EA is held low, the CPU executes only out
of external Program Memory. EA must not be floated.
Idle And Power Down Operation
Figure 3. shows the internal Idle and Power Down clock
configuration. As illustrated, Power Down operation
stops the oscillator. Idle mode operation allows the
interrupt, serial port, and timer blocks to continue to
function, while the clock to the CPU is gated off.
These special modes are activated by software via the
Special Function Register, PCON. Its hardware address is
87H. PCON is not bit addressable.
Figure 3. Idle and Power Down Hardware.
PCON : Power Control Register
(MSB)
(LSB)
SMOD – – – GF1 GF0 PD IDL
Symbol
Position
Name and Function
SMOD
–
–
–
GF1
GF0
PD
IDL
PCON.7
PCON.6
PCON.5
PCON.4
PCON.3
PCON.2
PCON.1
PCON.0
Double Baud rate bit. When set to
a 1, the baud rate is doubled when
the serial port is being used in
either modes 1, 2 or 3.
(Reserved)
(Reserved)
(Reserved)
General-purpose flag bit.
General-purpose flag bit.
Power Down bit. Setting this bit
activates power down operation.
Idle mode bit. Setting this bit
activates idle mode operation.
If 1’s are written to PD and IDL at the same time. PD
takes, precedence. The reset value of PCON is
(000X0000).
Idle Mode
The instruction that sets PCON.0 is the last instruction
executed before the Idle mode is activated. Once in the
Idle mode the CPU status is preserved in its entirety : the
Stack Pointer, Program Counter, Program Status Word,
Accumulator, RAM and all other registers maintain their
data during idle. Table 1 describes the status of the
external pins during Idle mode.
There are three ways to terminate the Idle mode.
Activation of any enabled interrupt will cause PCON.0 to
be cleared by hardware, terminating Idle mode. The
interrupt is serviced, and following RETI, the next
instruction to be executed will be the one following the
instruction that wrote 1 to PCON.0.
MATRA MHS
Rev. E (14 Jan.97)
5
www.DataSheet.in
5 Page 
TSC80C31/80C51
Absolute Maximum Ratings*
Ambient Temperature Under Bias :
M = Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to + 150°C
Voltage on VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to + 7 V
Voltage on Any Pin to VSS . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W**
** This value is based on the maximum allowable die temperature and
the thermal resistance of the package
* Notice
Stresses at or above those listed under “ Absolute Maximum Ratings”
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
DC Parameters
TA = –55°C + 125°C ; Vss = 0 V ; Vcc = 5 V ± 10 % ; F = 0 to 40 MHz
Symbol
Parameter
Min Typ (3) Max Unit Test Conditions
VIL Input Low Voltage
VIH Input High Voltage (Except XTAL and RST)
VIH1 Input High Voltage (for XTAL and RST)
VOL Output Low Voltage (Port 1, 2 and 3) (4)
VOL1 Output Low Voltage (Port 0, ALE, PSEN) (4)
VOH Output High Voltage (Port 1, 2 and 3)
– 0.5
0.2 Vcc + 0.9
0.7 Vcc
2.4
VOH1 Output High Voltage
(Port 0 in External Bus Mode, ALE, PEN)
IIL Logical 0 Input Current (Ports 1, 2 and 3)
ILI Input leakage Current
ITL Logical 1 to 0 Transition Current (Ports 1, 2 and 3)
IPD Power Down Current
RRST RST Pulldown Resistor
CIO Capacitance of I/O Buffer
ICC Power Supply Current
Freq = 1 MHz Icc op
Icc idle
Freq = 6 MHz Icc op
Icc idle
Freq ≥ 12 MHz Icc op max = 0.9 Freq (MHz) + 5
Icc idle max = 0.3 Freq (MHz) + 1.7
Freq ≤ 20 MHz Icc op typ = 0.7 Freq (MHz)
Freq ≥ 20 MHz Icc op typ = 0.5 Freq (MHz) + 4
Freq ≤ 20 MHz Icc idle typ = 0.16 Freq (MHz) + 0.4
Freq ≥ 20 MHz Icc idle typ = 0.12 Freq (MHz) + 1.2
0.75 Vcc
0.9 Vcc
2.4
0.75 Vcc
0.9 Vcc
50
0.2 Vcc – 0.1 V
Vcc + 0.5 V
Vcc + 0.5 V
0.45 V IOL = 1.6 mA (2)
0.45 V IOL = 3.2 mA (2)
V IOH = – 60 µA
Vcc = 5 V ± 10 %
V IOH = – 25 µA
V IOH = – 10 µA
V IOH = – 400 µA
Vcc = 5 V ± 10 %
V IOH = – 150 µA
V IOH = – 40 µA
– 75 µA Vin = 0.45 V
+/– 10
µA 0.45 < Vin < Vcc
– 750
µA Vin = 2.0 V
5 75 µA Vcc = 2.0 V to 5.5 V (1)
90 200 KΩ
10 pF fc = 1 MHz, Ta = 25_C
Vcc = 5.5 V
0.7 1.8 mA
0.5 1 mA
4.2 9 mA
1.4 3.5 mA
mA
mA
mA
mA
mA
mA
MATRA MHS
Rev. E (14 Jan.97)
www.DataSheet.in
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet TSC80C31.PDF ] | |
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