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PDF ADC11DS105 Data sheet ( Hoja de datos )
| Número de pieza | ADC11DS105 | |
| Descripción | 105 MSPS A/D Converter | |
| Fabricantes | National Semiconductor | |
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ADC11DS105
November 4, 2009
Dual 11-Bit, 105 MSPS A/D Converter with Serial LVDS
Outputs
General Description
The ADC11DS105is a high-performance CMOS analog-to-
digital converters capable of converting two analog input
signals into 11-bit digital words at rates up to 105 Mega Sam-
ples Per Second (MSPS). The digital outputs are serialized
and provided on differential LVDS signal pairs. These con-
verters use a differential, pipelined architecture with digital
error correction and an on-chip sample-and-hold circuit to
minimize power consumption and the external component
count, while providing excellent dynamic performance. The
ADC11DS105 may be operated from a single +3.0 or +3.3V
power supply. A power-down feature reduces the power con-
sumption to very low levels while still allowing fast wake-up
time to full operation. The differential inputs accept a 2V full
scale differential input swing. A stable 1.2V internal voltage
reference is provided, or the ADC11DS105 can be operated
with an external 1.2V reference. The selectable duty cycle
stabilizer maintains performance over a wide range of clock
duty cycles. A serial interface allows access to the internal
registers for full control of the ADC11DS105's functionality.
The ADC11DS105 is available in a 60-lead LLP package and
operates over the industrial temperature range of −40°C to
+85°C.
Features
■ Clock Duty Cycle Stabilizer
■ Single +3.0 or +3.3V supply operation
■ Serial LVDS Outputs
■ Serial Control Inteface
■ Overrange Outputs
■ 60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch)
Key Specifications
■ Resolution
■ Conversion Rate
■ SNR (fIN = 240 MHz)
■ SFDR (fIN = 240 MHz)
■ Full Power Bandwidth
■ Power Consumption
11 Bits
105 MSPS
66 dBFS (typ)
82 dBFS (typ)
1 GHz (typ)
1 W (typ)
Applications
■ High IF Sampling Receivers
■ Wireless Base Station Receivers
■ Test and Measurement Equipment
■ Communications Instrumentation
■ Portable Instrumentation
Connection Diagram
© 2009 National Semiconductor Corporation 300293
www.DataSheet.in
30029301
www.national.com
1 page  
Pin No.
Symbol
38 SD1_A+
37 SD1_A-
34 SD1_B+
33 SD1_B-
36 SD0_A+
35 SD0_A-
32 SD0_B+
31 SD0_B-
56 SPI_EN
55 SCSb
52 SCLK
54 SDI
Equivalent Circuit
Description
Serial Data Output 1 for Channel A. This is a differential LVDS pair
of signals that carries channel A ADC’s output in serialized form.
The serial data is provided synchronous with the OUTCLK output.
In Single-Lane mode each sample’s output is provided in
succession. In Dual-Lane mode every other sample output is
provided on this output. This differential output is always enabled
while the device is powered up. In power-down mode this output
holds the last logic state. A 100-ohm termination resistor must
always be used between this pair of signals at the far end of the
transmission line.
Serial Data Output 1 for Channel B. This is a differential LVDS pair
of signals that carries channel B ADC’s output in serialized form.
The serial data is provided synchronous with the OUTCLK output.
In Single-Lane mode each sample’s output is provided in
succession. In Dual-Lane mode every other sample output is
provided on this output. This differential output is always enabled
while the device is powered up. In power-down mode this output
holds the last logic state. A 100-ohm termination resistor must
always be used between this pair of signals at the far end of the
transmission line.
Serial Data Output 0 for Channel A. This is a differential LVDS pair
of signals that carries channel A ADC’s alternating samples’ output
in serialized form in Dual-Lane mode. The serial data is provided
synchronous with the OUTCLK output. In Single-Lane mode this
differential output is held in high impedance state. This differential
output is always enabled while the device is powered up. In power-
down mode this output holds the last logic state. A 100-ohm
termination resistor must always be used between this pair of
signals at the far end of the transmission line.
Serial Data Output 0 for Channel B. This is a differential LVDS pair
of signals that carries channel B ADC’s alternating samples’ output
in serialized form in Dual-Lane mode. The serial data is provided
synchronous with the OUTCLK output. In Single-Lane mode this
differential output is held in high impedance state. This differential
output is always enabled while the device is powered up. In power-
down mode this output holds the last logic state. A 100-ohm
termination resistor must always be used between this pair of
signals at the far end of the transmission line.
SPI Enable: The SPI interface is enabled when this signal is
asserted high. In this case the direct control pins have no effect.
When this signal is deasserted, the SPI interface is disabled and
the direct control pins are enabled.
Serial Chip Select: While this signal is asserted SCLK is used to
accept serial data present on the SDI input and to source serial
data on the SDO output. When this signal is deasserted, the SDI
input is ignored and the SDO output is in tri-state mode.
Serial Clock: Serial data are shifted into and out of the device
synchronous with this clock signal.
Serial Data-In: Serial data are shifted into the device on this pin
while SCSb signal is asserted.
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5 Page 
Specification Definitions
APERTURE DELAY is the time after the falling edge of the
clock to when the input signal is acquired or held for conver-
sion.
APERTURE JITTER (APERTURE UNCERTAINTY) is the
variation in aperture delay from sample to sample. Aperture
jitter manifests itself as noise in the output.
CLOCK DUTY CYCLE is the ratio of the time during one cycle
that a repetitive digital waveform is high to the total time of
one period. The specification here refers to the ADC clock
input signal.
COMMON MODE VOLTAGE (VCM) is the common DC volt-
age applied to both input terminals of the ADC.
CONVERSION LATENCY is the number of clock cycles be-
tween initiation of conversion and when that data is presented
to the output driver stage. Data for any given sample is avail-
able at the output pins the Pipeline Delay plus the Output
Delay after the sample is taken. New data is available at every
clock cycle, but the data lags the conversion by the pipeline
delay.
CROSSTALK is coupling of energy from one channel into the
other channel.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio or SINAD. ENOB is defined as (SINAD -
1.76) / 6.02 and says that the converter is equivalent to a
perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated as:
Gain Error = Positive Full Scale Error − Negative Full Scale
Error
It can also be expressed as Positive Gain Error and Negative
Gain Error, which are calculated as:
PGE = Positive Full Scale Error - Offset Error
NGE = Offset Error - Negative Full Scale Error
INTEGRAL NON LINEARITY (INL) is a measure of the de-
viation of each individual code from a best fit straight line. The
deviation of any given code from this straight line is measured
from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the intermodulation
products to the total power in the original frequencies. IMD is
usually expressed in dBFS.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the small-
est value or weight of all bits. This value is VFS/2n, where
“VFS” is the full scale input voltage and “n” is the ADC reso-
lution in bits.
LVDS Differential Output Voltage (VOD) is the absolute val-
ue of the difference between the differential output pair volt-
ages (VD+ and VD-), each measured with respect to ground.
LVDS Output Offset Voltage (VOS) is the midpoint between
the differential output pair voltages.
MISSING CODES are those output codes that will never ap-
pear at the ADC outputs. The ADC is guaranteed not to have
any missing codes.
MSB (MOST SIGNIFICANT BIT) is the bit that has the largest
value or weight. Its value is one half of full scale.
NEGATIVE FULL SCALE ERROR is the difference between
the actual first code transition and its ideal value of ½ LSB
above negative full scale.
OFFSET ERROR is the difference between the two input
voltages [(VIN+) – (VIN-)] required to cause a transition from
code 1023 to 1024.
OUTPUT DELAY is the time delay after the falling edge of the
clock before the data update is presented at the output pins.
PIPELINE DELAY (LATENCY) See CONVERSION LATEN-
CY.
POSITIVE FULL SCALE ERROR is the difference between
the actual last code transition and its ideal value of 1½ LSB
below positive full scale.
POWER SUPPLY REJECTION RATIO (PSRR) is a measure
of how well the ADC rejects a change in the power supply
voltage. PSRR is the ratio of the Full-Scale output of the ADC
with the supply at the minimum DC supply limit to the Full-
Scale output of the ADC with the supply at the maximum DC
supply limit, expressed in dB.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the sam-
pling frequency, not including harmonics or DC.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or
SINAD) Is the ratio, expressed in dB, of the rms value of the
input signal to the rms value of all of the other spectral com-
ponents below half the clock frequency, including harmonics
but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB, between the rms values of the input
signal and the peak spurious signal, where a spurious signal
is any signal present in the output spectrum that is not present
at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-
pressed in dB, of the rms total of the first six harmonic levels
at the output to the level of the fundamental at the output. THD
is calculated as
where f1 is the RMS power of the fundamental (output) fre-
quency and f2 through f7are the RMS power of the first six
harmonic frequencies in the output spectrum.
SECOND HARMONIC DISTORTION (2ND HARM) is the dif-
ference expressed in dB, between the RMS power in the input
frequency at the output and the power in its 2nd harmonic
level at the output.
THIRD HARMONIC DISTORTION (3RD HARM) is the dif-
ference, expressed in dB, between the RMS power in the
input frequency at the output and the power in its 3rd harmonic
level at the output.
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| PDF Descargar | [ Datasheet ADC11DS105.PDF ] | |
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