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PDF AL2007LA Data sheet ( Hoja de datos )
| Número de pieza | AL2007LA | |
| Descripción | Phase-Locked Loop | |
| Fabricantes | Samsung semiconductor | |
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0.35µm 20MHZ-170MHZ FSPLL
AL2007LA
GENERAL DESCRIPTION
The AL2007LA is a Phase-Locked Loop (PLL) frequency synthesizer constructed in CMOS on single monolithic
structure. The PLL macrofunctions provide frequency multiplication capabilities.
The output clock frequency Fout is related to the reference input clock frequency Fin by the following equation:
Fout = ( m*Fin ) / ( p* 2S)
Where, Fout is the output clock frequency. Fin is the reference input clock frequency. m,p and s are the values for
programmable dividers. AL2007LA consists of a phase/Frequency Detector(PFD), a Charge Pump an External
Loop Filter, a Voltage Controlled Oscillator(VCO), a 6bit Pre-divider, an 8bit Main divider and 2bit Post Scaler as
shown in Figure1.
FEATURES
— 0.35um CMOS device technology
— 3.3 Volt Single power supply
— VCO frequency range: 60~170MHz
— Output frequency range: 20~170MHz
— Jitter ±150ps
— Duty ratio 40% to 60% at 170MHz
— Frequency changed by programmable divider
— Power down mode
IMPORTANT NOTICE
Please contact SEC application engineer to confirm the proper selection of M,P,S value.
FUNCTIONAL BLOCK DIAGRAM
Pre Divider
Fin P
PFD
Charge
Pump
Loop
Filter
(External)
VCO
Fout
Post Scaler
S
www.DataSheet.in
Main Divider
M
Figure 1. Phase Lockd Loop Block Diagram
1
1 page  
0.35µm 20MHZ-170MHZ FSPLL
AL2007LA
DC ELECTRICAL CHARACTERISTICS
Characteristics
Symbol
Min
Typ
Max
Unit
Operating Voltage
VDD/VDDA
3.15
3.3
3.45
V
Digital Input Voltage High
Vih 2.0
V
Digital Input Voltage Low
Vil
0.8 V
Dynamic Current
(CORE Level without I/O Cell)
Idd
3.5 mA
Power Down Current
Ipd
120 uA
AC ELECTRICAL CHARACTERISTICS
Characteristics
Input Frequency
Output Clock Frequency
VCO Output Clock Frequency
Input Clock Duty Cycle
Output Clock Duty Cycle
Locking Time
Cycle to Cycle Jitter
Symbol
FIN
FOUT
Fvco
TID
TOD
TLT
TJCC
Min
3
20
20
40
40
-150
Typ
14.318
Max
40
170
170
60
60
150
+150
Unit
MHz
MHz
MHz
%
%
us
ps
www.DataSheet.in
5
5 Page 
0.35µm 20MHZ-170MHZ FSPLL
PACKAGE CONFIGURATION
AL2007LA
2bit Post Scaler Dummy Test Block Control pins
3.3V Digital PAD Power
C
LL LL
3.3V I/O Power
H H H HC
36 35 34 33 32 31 30 29 28 27 26 25
V V VV S S T T V V NN
8bit Main Divider
D D S S 0 1 S S D S CC
DD SS
EE DS
LH
37 M0 D D D D
LL OO
NC 24
01
LH
38 M1
FOUT 23
LH
LH
39 M2
40 M3
al2007la
NC 22
NC 21
LH
41 M4
VBBA 20
LH
LH
LH
42 M5
43 M6
44 M7
C
10uF
103
VBBA 19
PWRDN 18
FILTER 17
H
820pF
L
LH
LH
45 P0
46 P1
NC 16
FIN 15
External Clock Source
LH
47 P2
LH
48 P3
6bit Pre Divider Input
P
4
P N NN N
5 C CC C
VDDA 14
V VVDDA 13
C
SS
NNNN S S
3.3V Analog Power
CCCC A A
12
3 45
6 7 8 9 10 11 12
HH
LL
NOTES:
1. TSEL0,TSEL1 pins are internal dummy block test pins.
2. NC is Noconnection pin
www.DataSheet.in
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AL2007LA.PDF ] | |
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