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PDF ISL6265C Data sheet ( Hoja de datos )
| Número de pieza | ISL6265C | |
| Descripción | Multi-Output Controller | |
| Fabricantes | Intersil Corporation | |
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Multi-Output Controller with Integrated MOSFET
Drivers for AMD SVI Capable Mobile CPUs
ISL6265C
The ISL6265C is a multi-output controller with embedded
gate drivers. A single-phase controller powers the
Northbridge (VDDNB) portion of the CPU. The two
remaining controller channels can be configured for
two-phase or individual single-phase outputs. For
uniplane CPU applications, the ISL6265C is configured as
a two-phase buck converter. This allows the controller to
interleave channels to effectively double the output
voltage ripple frequency, and thereby reduce output
voltage ripple amplitude with fewer components, lower
component cost, reduced power dissipation, and smaller
area. For dual-plane processors, the ISL6265C can be
configured as independent single-phase controllers
powering VDD0 and VDD1.
The heart of the ISL6265C is the patented R3
Technology™, Intersil’s Robust Ripple Regulator
modulator. Compared with the traditional buck regulator,
the R3 Technology™ has a faster transient response. This
is due to the R3 modulator commanding variable
switching frequency during a load transient.
The Serial VID Interface (SVI) allows dynamic
adjustment of the Core and Northbridge output voltages
independently and in combination from 0.500V to 1.55V.
Core and Northbridge output voltages achieve a 0.5%
system accuracy over-temperature.
A unity-gain differential amplifier is provided for remote
CPU die sensing. This allows the voltage on the CPU die
to be accurately regulated per AMD mobile CPU
specifications. Core output current sensing is realized
using lossless inductor DCR sensing. All outputs feature
overcurrent, overvoltage and undervoltage protection.
Features
• Core Configuration Flexibility
- Dual Plane, Single-Phase Controllers
- Uniplane, Two-Phase Controller
• Precision Voltage Regulators
- 0.5% System Accuracy Over-temperature
• Voltage Positioning with Adjustable Load Line and Offset
• Internal Gate Drivers with 2A Driving Capability
• Differential Remote CPU Die Voltage Sensing
• Core Differential Current Sensing: DCR or Resistor
• Northbridge Lossless rDS(ON) Current Sensing
• Serial VID Interface
- Two Wire Clock and Data Bus
- Supports High-Speed I2C
- 0.500V to 1.55V in 12.5mV Steps
- Supports PSI_L Power-Saving Mode
• Core Outputs Feature Phase Shedding with PSI_L
• Adjustable Output-Voltage Offset
• Digital Soft-Start of all Outputs
• User Programmable Switching Frequency
• Static and Dynamic Current Sharing (Uniplane Core)
• Overvoltage, Undervoltage, and Overcurrent Protection
• Pb-Free (RoHS compliant)
Applications*(see page 26)
• AMD Griffin Platform CPU
• Notebook Core/GPU Voltage Regulators
Related Literature*(see page 26)
• See FN6884 for “Multi-Output Controller with Integrated
MOSFET Drivers for AMD SVI Capable Mobile CPUs”
Simplified System Diagram
POWER
STAGE
CORE_0
ISL6265C
POWER
STAGE
CORE_1
POWER
STAGE
July 28, 2010
FN6976.1
www.DataSheet.in
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6265C
Pin Descriptions (Continued)
PIN(s)
34, 26
SYMBOL(s)
UGATE0, UGATE1
DESCRIPTION
Connect these pins to the corresponding upper MOSFET gate(s). These pins control the
upper MOSFET gate(s) and are monitored for shoot-through prevention.
35, 25
BOOT0, BOOT1
These pins provide the bias voltage for the corresponding upper MOSFET drives. Connect
these pins to appropriately chosen external bootstrap capacitors. Internal bootstrap
diodes connected to the PVCC pin provide the necessary bootstrap charge.
36
BOOT_NB
This pin is the upper gate drive supply voltage for the Northbridge controller. Connect an
appropriately sized ceramic bootstrap capacitor between the BOOT_NB and PHASE_NB
pins. An internal bootstrap diode connected to the PVCC pin provides the necessary
bootstrap charge.
37
UGATE_NB
Upper MOSFET gate signal from Northbridge controller.
38
PHASE_NB
Switch node of the Northbridge controller. This pin should connect to the source of the
Northbridge channel upper MOSFET(s).
39
LGATE_NB
Lower MOSFET gate signal from Northbridge controller.
40
PGND_NB
The return path of the Northbridge controller lower gate driver. Connect this pin to the
source of the lower MOSFET(s).
41
OCSET_NB
Overcurrent protection selection input for the Northbridge controller. A resistor from this
pin to PHASE_NB sets the OC trip point.
43, 42
VSEN_NB, RTN_NB Remote Northbridge voltage sense input and return. Connect isolated traces from these
pins to the Northbridge sense points of the processor.
44
FSET_NB
A resistor from this pin to GND programs the switching frequency of the Northbridge
controller (for example, 22.1k ~ 260kHz).
45
COMP_NB
This pin is the output of the Northbridge controller error amplifier.
46
FB_NB
This pin is the output voltage feedback to the inverting input of the Northbridge controller
error amplifier.
47
VCC
The bias supply for the IC’s control circuitry. Connect this pin to a +5V supply and
decouple using a quality 0.1µF ceramic capacitor.
48 VIN Battery supply voltage. It is used for input voltage feed-forward to improve the input line
transient performance.
-
GND
The bias and reference ground for the IC. The GND connection for the ISL6265C is
through the thermal pad on the bottom of the package.
www.DataSheet.in
5
FN6976.1
July 28, 2010
5 Page 
ISL6265C
Electrical Specifications VCC = PVCC = 5V, VIN = 12V, TA = -10°C to +100°C, Unless Otherwise Specified. Boldface
limits apply over the operating temperature range, -10°C to +100°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 6) TYP (Note 6) UNITS
Error Amp Gain-Bandwidth
Product (Note 7)
GBW
CL = 20pF
- 18 - MHz
Error Amp Slew Rate (Note 7)
CORE CURRENT SENSE
SR CL = 20pF
- 5.0 - V/µs
Current Imbalance Threshold
Di
- 4 - mV
Input Bias Current
- 20 - nA
RTN1 Threshold
- 0.8 -
V
SOFT START/VID-ON-THE-FLY
Soft-Start Voltage Transition
VID on the Fly Transition
VSS
1.25
5
1.875
7.5
2.50
10
mV/µs
mV/µs
GATE DRIVER DRIVING CAPABILITY [CORE AND NB]
UGATE Source Resistance
(Note 8)
RSRC(UGATE) 500mA Source Current
- 1 1.5 Ω
UGATE Source Current (Note 8)
UGATE Sink Resistance (Note 8)
UGATE Sink Current (Note 8)
LGATE Source Resistance
(Note 8)
ISRC(UGATE) VUGATE_PHASE = 2.5V
RSNK(UGATE) 500mA Sink Current
ISNK(UGATE) VUGATE_PHASE = 2.5V
RSRC(LGATE) 500mA Source Current
-2-A
- 1 1.5 Ω
-2-A
- 1 1.5 Ω
LGATE Source Current (Note 8) ISRC(LGATE) VLGATE = 2.5V
-2-
LGATE Sink Resistance (Note 8) RSNK(LGATE) 500mA Sink Current
- 0.5 0.9
LGATE Sink Current (Note 8) ISNK(LGATE) VLGATE = 2.5V
-4-
UGATE to PHASE Resistance
Rp(UGATE)
-1-
GATE DRIVER SWITCHING TIMING (Refer to “ISL6265C Gate Driver Timing Diagram” on page 13)
A
Ω
A
kΩ
UGATE Rise Time (Note 7)
LGATE Rise Time (Note 7)
UGATE Fall Time (Note 7)
LGATE Fall Time (Note 7)
UGATE Turn-on Propagation
Delay
tRU
tRL
tFU
tFL
tPDHU
PVCC = 5V, 3nF Load
PVCC = 5V, 3nF Load
PVCC = 5V, 3nF Load
PVCC = 5V, 3nF Load
PVCC = 5V, Outputs Unloaded
- 8.0 -
- 8.0 -
- 8.0 -
- 4.0 -
- 36 -
ns
ns
ns
ns
ns
LGATE Turn-on Propagation
Delay
tPDHL
PVCC = 5V, Outputs Unloaded
- 20 - ns
BOOTSTRAP DIODE
Forward Voltage
VDDP = 5V, Forward Bias
Current = 2mA
0.43
0.58
0.67
V
Leakage
VR = 16V
POWER-GOOD AND PROTECTION MONITOR
- - 5 µA
PGOOD Low Voltage
PGOOD Leakage Current
PGOOD High After Soft-Start
PGOOD Low After Fault
VOL
IPGOOD = 4mA
-
IOH PGOOD = 5V
-1
Enable to PGOOD High, VCOREx = 1.1V 570
Fault to PGOOD Low
160
0.2 0.5
-1
700 1010
208 250
V
µA
µs
µs
Undervoltage Threshold
UVH
VCOREx falls below set-point for 208µs
240
295
350
mV
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11
FN6976.1
July 28, 2010
11 Page | ||
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| PDF Descargar | [ Datasheet ISL6265C.PDF ] | |
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