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PDF UTC3842A Data sheet ( Hoja de datos )
| Número de pieza | UTC3842A | |
| Descripción | (UTC3842A /UTC3843A) CURRENT MODE PWM CONTROL CIRCUITS | |
| Fabricantes | UNISONIC TECHNOLOGIES | |
| Logotipo |  |
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DataSheet.in
UTCUC3842A/3843A LINEARINTEGRATEDCIRCUIT
CURRENT MODE PWM CONTROL
CIRCUITS
DESCRIPTION
The UTC UC3842A/3843A provide the necessary functions
to implement off-line or DC to DC fixed frequency current
mode , controlled switching circuits with a minimal external
part count
SOP-8
FEATURES
*Low external part count.
*Low start up current ( Typical 0.12mA )
*Automatic feed forward compensation
*Pulse-by-Pulse current limiting
*Under-voltage lockout with hysteresis
*Double pulse Suppression
*High current totem pole output to drive MOSFET directly
*Internally trimmed band gap reference
*500kHz operation
BLOCK DIAGRAM
Vref 8
Internal
Bias
VFB 2
COMP 1
CURRENT SENSE 3
RT/CT 4
1/2Vref
ERROR
AMPLIFIER
5V REF
S/R
Vref
Good
Logic
1/3Vref
U.V.L.O
CURRENT
SENSE
COMPARATOR
1V R
PWM
LATCH
S
OSCILLATOR
DIP-8
7 Vcc
5 GND
7 Vcc
6 OUTPUT
5 GND
ABSOLUTE MAXIMUM RATINGS(Ta=25°C)
PARAMETER
SYMBOL
Supply Voltage(Low Impedance Source)
VCC
Supply Voltage(Icc<30mA)
Vcc
Output Current ( Peak )
Io
Output Energy(capacity Load)
Analog Inputs(pin 2,3)
VI(ANA)
Error Amplifier Output Sink Current
ISINK(EA)
Power Dissipation
PD DIP-8
SOP-8
Lead Temperature( Soldering 10 Sec )
Tlead
VALUE
30
Self Limiting
+-1
5
-0.3 ~ +6.3
10
at Tamb<=25°C 1.0
at Tamb<=25°C 0.5
300
UNIT
V
V
A
µJ
V
mA
W
W
°C
UTC UNISONIC TECHNOLOGIES CO., LTD.
1
QW-R103-002,B
1 page  
DataSheet.in
UTCUC3842A/3843A LINEARINTEGRATEDCIRCUIT
OSCILLATOR SECTION
8
4
5
Large RT
Small CT
RT
CT Small RT
Large CT
V4
INTERNAL
CLOCK
V4
INTERNAL
CLOCK
100
td (µs)
10
1
0.1
1
Dead time VS CT(RT>5kΩ) Timing Resistance Vs Frequency
10 100
CT (nF)
100
RT (kΩ)
10
1
10 2
CT=1nF
CT=2.2nF
CT=4.7nF
CT=10nF
CT=22nF
CT=47nF
CT=100nF
103 104 105
Frequency (Hz)
10 6
SHUTDOWN TECHNIQUES
1kΩ 8
Shutdown
Shutdown
3
To current
Sense resistor
1
Shutdown UTC UC3842A can be
accomplished by two methods; either raise pin 3
above 1V or pull Pin 1 below a voltage two diode
drops above ground. Either method caused the
output of PWM comparator to be high(refer to
block diagram).The PWM latch is reset dominant
so that the output will remain low until the next
clock cycle after the shutdown condition at pins 1
and/or 3 is removed . In one example, an
externally latched shut –down may be
accomplished by adding an SCR which be reset
by cycling Vcc below the lower UVLO threshold.
At this point the reference turns off allowing the
SCR to reset.
UTC UNISONIC TECHNOLOGIES CO. LTD 5
QW-R103-002,B
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet UTC3842A.PDF ] | |
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