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PDF H57V2562GFR Data sheet ( Hoja de datos )
| Número de pieza | H57V2562GFR | |
| Descripción | 256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O
www.DataSheet4U.com
256M (16Mx16bit) Hynix SDRAM
Memory
Memory Cell Array
- Organized as 4banks of 4,194,304 x 16
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.0 / Aug. 2009
1
1 page  
111www.DataSheet4U.com
Synchronous DRAM Memory 256Mbit
H57V2562GFR Series
BALL CONFIGURATION
98
7
A
B
C
D
E
F
G
H
J
3 21
54 Ball
FBGA
0.8mm
Ball Pitch
1
VSS
DQ14
DQ12
DQ10
DQ8
UDQM
A12
A8
VSS
2
DQ15
DQ13
DQ11
DQ9
NC
CLK
A11
A7
A5
<Bottom View>
37
VSSQ A VDDQ
VDDQ B VSSQ
VSSQ C VDDQ
VDDQ D VSSQ
VSS E VDD
CKE F /CAS
A9 G BA0
A6 H A0
A4 J A3
< Top View >
8
DQ0
DQ2
DQ4
DQ6
LDQM
/RAS
BA1
A1
A2
9
VDD
DQ1
DQ3
DQ5
DQ7
/WE
/CS
A10
VDD
Rev 1.0 / Aug. 2009
5
5 Page 
111w w w . D a t a S h e e t 4 U . c o m
Synchronous DRAM Memory 256Mbit
H57V2562GFR Series
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter
Speed
(MHz)
System Clock Cycle Time
CL = 3
CL = 2
Clock High Pulse Width
Clock Low Pulse Width
Access Time From Clock
CL = 3
CL = 2
Data-out Hold Time
Data-Input Setup Time
Data-Input Hold Time
Address Setup Time
Address Hold Time
CKE Setup Time
CKE Hold Time
Command Setup Time
Command Hold Time
CLK to Data Output in Low-Z Time
CLK to Data Output in CL = 3
High-Z Time
CL = 2
tCK3
tCK2
tCHW
tCLW
tAC3
tAC2
tOH
tDS
tDH
tAS
tAH
tCKS
tCKH
tCS
tCH
tOLZ
tOHZ3
tOHZ2
166
Min Max
6.0 1000
- 1000
2.5 -
2.5 -
- 5.4
--
2.0 -
1.5 -
0.8 -
1.5 -
0.8 -
1.5 -
0.8 -
1.5 -
0.8 -
1.0 -
2.7 5.4
--
133
Min Max
7.5 1000
10 1000
2.5 -
2.5 -
- 5.4
-6
2.5 -
1.5 -
0.8 -
1.5 -
0.8 -
1.5 -
0.8 -
1.5 -
0.8 -
1.0 -
2.7 5.4
36
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1
1
2
2
1
1
1
1
1
1
1
1
Note:
1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added
to the parameter.
Rev 1.0 / Aug. 2009
11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet H57V2562GFR.PDF ] | |
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