92RB25 Datasheet PDF - Oki Semiconductor
| Part Number | 92RB25 | |
| Description | MSM92RB25 | |
| Manufacturers | Oki Semiconductor | |
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DATA SHEET
OKI
ASIC
www.DataSheet4U.com
PRODUCTS
MSM30R/32R/92R
0.5µm Sea Of Gates and
Customer Structured Arrays
August 2002
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––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– I MSM30R/32R/92R I
www.DataSheet4U.com
ARRAY ARCHITECTURE
The primary components of a 0.5µm MSM30R/32R/92R circuit include:
• I/O base cells
• Configurable I/O pads for VDD, VSS, or I/O (optimized 3-V I/O and 3-V I/O that is 5-V tolerant)
• VDD and VSS pads dedicated to wafer probing
• Separate power bus for output buffers
• Separate power bus for internal core logic and input buffers
• Core base cells containing N-channel and P-channel pairs, arranged in column of gates
• Isolated gate structure for reduced input capacitance and increased routing flexibility
Each array has 24 dedicated corner pads for power and ground use during wafer probing, with four pads
per corner. The arrays also have separate power rings for the internal core functions (VDDC and VSSC)
and output drive transistors (VDDO and VSSO).
Configurable I/O pads
for VDD, VSS, or I/O
I/O base cells
Separate power bus (VDDC, VSSC) for
internal core logic (2nd metal/3rd metal
1,2, or 3 layer metal
interconnection in
core area
Core base cell
with 4 transistors
VDD, VSS pads (4) in each
corner for
wafer probing only
Separate power bus (VDDO, VSSO)
over I/O cell for output buffers(2nd
metal/3rd metal)
Figure 7. MSM30R0000 Array Architecture
MSM92R000 CSA Layout Methodology
The procedure to design, place, and route a CSA follows.
1. Select suitable base array frame from the available predefined sizes. To select an array size:
- Identify the macrocell functions required and the minimum array size to hold the macrocell
functions.
Oki Semiconductor
3
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| Information | Total 22 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
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| Part Number | Description | MFRS |
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