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PDF 73S8010C Data sheet ( Hoja de datos )
| Número de pieza | 73S8010C | |
| Descripción | Smart Card Interface | |
| Fabricantes | Teridian Semiconductor | |
| Logotipo |  |
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Simplifying System Integration™
www.DataSheet4U.com
73S8010C
Smart Card Interface
DATA SHEET
April 2009
DESCRIPTION
The Teridian 73S8010C is a single smart card
interface IC. It provides full electrical compliance
with ISO-7816-3 and EMV 4.0 specifications.
Interfacing with the host is done through the two-wire
I2C bus. Data exchange with the card is managed
from the system controller using the I/O line (and
eventually the auxiliary I/O lines).
An on-chip oscillator using an external crystal, or
connection to a clock signal coming from the
system controller can generate the card clock
signal.
The 73S8010C IC incorporates an ISO-7816-3
activation/deactivation sequencer that controls the
card signals. Level shifters drive the card signals
with the selected card voltage (3 V or 5 V), coming
from an internal DC-DC converter.
With its high-efficiency DC-DC converter, the
Teridian 73S8010C is a cost-effective solution for
any smart card reader application to be powered
from a single 2.7 V to 3.6 V power supply.
Hardware support for auxiliary I/O lines, C4 / C8
contacts, is provided.
Emergency card deactivation is initiated upon card
extraction or upon any fault generated by the
protection circuitry. The fault can be a VDD (digital
power supply), a VCC (card power supply), a card
over-current, or an over-heating fault.
ADVANTAGES
Single smart card interface
The inductor-based DC-DC converter provides
higher current and efficiency than the usual
charge-pump capacitor-based converters
Ideal for battery-powered applications
Suitable for high current cards and
SAMs: (100 mA max)
Power down mode: 2 A typical
Small Format (5x5mm) 32-QFN package option
FEATURES
Card Interface:
Complies with ISO-7816-3 and EMV 4.0
A DC-DC Converter provides 3V / 5V to the
card from an external power supply input
High-efficiency converter: > 80% @ VDD= 3.3 V,
VCC = 5 V and ICC = 65 mA
Up to 100 mA supplied to the card
ISO-7816-3 Activation / Deactivation sequencer
with emergency automated deactivation on
card removal or fault detected by the protection
circuitry
Protection include 2 voltage supervisors that
detect voltage drops on card VCC and VDD
power supplies
The VDD voltage supervisor threshold value
can be externally adjusted
True over-current detection (150 mA max.)
1 card detection input
Auxiliary I/O lines, for C4 / C8 contact signals
Host Interface:
Fast mode, 400 kbps I2C slave bus
8 possible devices in parallel
One control register and one status register
Interrupt output to the host for fault
detection
Crystal oscillator or host clock, up to 27 MHz
Power Supply:
VDD: 2.7 V to 3.6 V
6 kV ESD Protection on the card interface
Package: SO28 or 32QFN
APPLICATIONS
Set-Top-Boxes, DVD / HDD Recorders:
Conditional Access and Pay-per-View slots
Point of Sales and Transaction Terminals
EMV slots in cell phones and PDAs
Rev. 1.5
© 2009 Teridian Semiconductor Corporation
1
1 page  
DS_8010C_024
73S8010CwwDwa.DtaataSShheeete4Ut .com
1 Pin Description
1.1 Card Interface
Name
I/O
AUX1
AUX2
RST
CLK
Pin
(SO)
11
13
12
16
15
PRES 10
VCC
17
GND
14
PIN
(QFN)
9
11
10
14
13
7
15
12
Description
Card I/O: Data signal to/from card. Includes a pull-up resistor to VCC.
AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC.
AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC.
Card reset: provides reset (RST) signal to card.
Card clock: provides clock (CLK) signal to card. The rate of this clock is
determined by the crystal oscillator frequency and CLKSEL bits in the
control register.
Card Presence switch: active high indicates card is present. Includes a
pull-down resistor.
Card power supply: logically controlled by sequencer, output of DC-DC
converter. Requires an external filter capacitor to the card GND.
Card ground.
1.2 Miscellaneous Inputs and Outputs
Name
XTALIN
XTALOUT
VDDF_ADJ
NC
PIN
(SO)
24
25
18
7, 9
PIN
(QFN)
23
24
17
4, 6, 8,
16, 25,
32
Description
Crystal oscillator input: can either be connected to a crystal or driven
as a source for the card clock.
Crystal oscillator output: connected to crystal. Left open if XTALIN is
being used as an external clock input.
VDD threshold adjustment input: this pin can be used to overwrite a
higher VDDF value (that controls deactivation of the card). Must be
left open if unused.
Non-connected pin.
1.3 Power Supply and Ground
Name
VDD
GND
GND
GND
LIN
PIN
(SO)
6, 21
4
14
22
5
Pin
(QFN)
3, 20
1
12
21
2
Description
System controller interface supply voltage: supply voltage for internal
circuitry and DC-DC converter power supply source.
DC-DC converter ground.
Smart Card I/O ground.
Digital ground.
External inductor: Connect external inductor from pin 5 to VDD. Keep the
inductor close to pin 5.
Rev. 1.5
5
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DS_8010C_024
73S8010CwwDwa.DtaataSShheeete4Ut .com
5 Voltage Supervision
Two voltage supervisors constantly check the level of the VDD and VCC voltages. A card deactivation
sequence is forced when a fault occurs for any of these voltage supervisors.
The digital circuitry is powered by the power supply applied on the VDD pin. VDD also defines the voltage
range to interface with the system controller. The VDD voltage supervisor is also used to initialize the
ISO-7816-3 sequencer at power-on, and to deactivate the card at power-off or when a fault occurs. The
voltage threshold of the VDD voltage supervisor is internally set by default to 2.3 V nominal. However, it
may be desirable in some applications, to modify this threshold value. The pin VDDF_ADJ (pin 18 in the
SO package, pin 17 in the QFN package) is used to connect an external resistor REXT1 to ground to raise
the VDD fault voltage to another value, VDDF (refer to Figure 11). The resistor value is defined as follows:
REXT = 180 kΩ / (VDDF - 2.33)
An alternative (more accurate) method of adjusting the VDD fault voltage is to use a resistive network of
R3 from the pin to supply and R4 from the pin to ground (see Figure 11). In order to set the new
threshold voltage, the equivalent resistance must be determined. This resistance value will be
designated Kx. Kx is defined as R4/(R4+R5). Kx is calculated as:
Kx = (2.649 / VTH) - 0.6042 where VTH is the desired new threshold voltage.
To determine the values of R4 and R5, use the following formulas.
R5 = 72000 / Kx
R4 = R5*(Kx / (1 – Kx))
Taking the example above, where a VDD fault threshold voltage of 2.7 V is desired, solving for Kx gives:
Kx = (2.649 / 2.7) - 0.6042 = 0.377.
Solving for R5 gives: R5 = 72000 / 0.377 = 191 k.
Solving for R4 gives: R4 = 191000 *(0.377 / (1 – 0.377)) = 115.6 k.
Using standard 1% resistor values gives R5 = 191 kand R4 = 115 kThese values give an equivalent
resistance of Kx = 0.376, a 0.3% error.
If the 2.3 V default threshold is used, the VDDF_ADJ pin must be left unconnected.
6 Power Down
A power down function is provided via the PWRDN pin (active high). When activated, the Power Down
(PD) mode disables all the internal analog functions, including the card analog interface, the oscillators
and the DC-DC converter, to put the 73S8010C in its lowest power consumption mode. PD mode is only
allowed in the deactivated condition (out of a card session, when the Start/Stop bit is set to 0 from the I2C
host controller).
The host controller invokes the power down state when it is desirable to save power. The signal PRES
remains functional in PD mode such that a card insertion sets INT high. The micro-controller must then
set PWRDN low and wait for the internal stabilization time prior to starting any card session (prior to
setting the Start/Stop bit to 1).
Resumption of the normal mode occurs approximately 10 ms (stabilization of the internal oscillators +
reset of the circuitry) after PWRDN is set low. No card activation should be invoked during this 10 ms
time period. If a card is present, INT can be used as an indication that the circuit has completed its
recovery from power down state. INT will go high at the end of the stabilization period. Should the
Start/Stop be set to 1 during PWRDN = 1, or within the 10 ms internal stabilization / reset time, it will not
be taken into account and the card interface will remain inactive. Since Start/Stop is taken into account
on its edges, it should be toggled low and high again after the 10 ms to activate a card.
Figure 5 illustrates the sequencing of the PD and Normal modes. PWRDN must be connected to GND if
the power down function is not used.
Rev. 1.5
11
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| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet 73S8010C.PDF ] | |
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