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PDF AT90USB162 Data sheet ( Hoja de datos )
| Número de pieza | AT90USB162 | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
– 125 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
• Non-volatile Program and Data Memories
– 8K / 16K Bytes of In-System Self-Programmable Flash
• Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
• USB boot-loader programmed by default in the factory
• In-System Programming by on-chip Boot Program hardware-activated after
reset
• True Read-While-Write Operation
– 512 Bytes EEPROM
• Endurance: 100,000 Write/Erase Cycles
– 512 Bytes Internal SRAM
– Programming Lock for Software Security
• USB 2.0 Full-speed Device Module with Interrupt on Transfer Completion
– Complies fully with Universal Serial Bus Specification REV 2.0
– 48 MHz PLL for Full-speed Bus Operation : data transfer rates at 12 Mbit/s
– Fully independant 176 bytes USB DPRAM for endpoint memory allocation
– Endpoint 0 for Control Transfers: from 8 up to 64-bytes
– 4 Programmable Endpoints:
• IN or Out Directions
• Bulk, Interrupt and IsochronousTransfers
• Programmable maximum packet size from 8 to 64 bytes
• Programmable single or double buffer
– Suspend/Resume Interrupts
– Microcontroller reset on USB Bus Reset without detach
– USB Bus Disconnection on Microcontroller Request
– USB pad multiplexed with PS/2 peripheral for single cable capability
• Peripheral Features
– PS/2 compliant pad
– One 8-bit Timer/Counters with Separate Prescaler and Compare Mode (two 8-bit
PWM channels)
– One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Mode
(three 8-bit PWM channels)
– USART with SPI master only mode and hardware flow control (RTS/CTS)
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
• On Chip Debug Interface (debugWIRE)
• Special Microcontroller Features
– Power-On Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
8-bit
Microcontroller
with
8/16K Bytes of
ISP Flash
and USB
Controller
AT90USB82
AT90USB162
7707F–AVR–11/10
1 page  
AT90USB82/162
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The AT90USB82/162 provides the following features: 8K / 16K bytes of In-System Programma-
ble Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, 22 general
purpose I/O lines, 32 general purpose working registers, two flexible Timer/Counters with com-
pare modes and PWM, one USART, a programmable Watchdog Timer with Internal Oscillator,
an SPI serial port, debugWIRE interface, also used for accessing the On-chip Debug system
and programming and five software selectable power saving modes. The Idle mode stops the
CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue func-
tioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling
all other chip functions until the next interrupt or Hardware Reset. In Standby mode, the Crys-
tal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast
start-up combined with low power consumption. In Extended Standby mode, the main Oscillator
continues to run.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The on-
chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programmer, or by an on-chip Boot program
running on the AVR core. The boot program can use any interface to download the application
program in the application Flash memory. Software in the Boot Flash section will continue to run
while the Application Flash section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,
the Atmel AT90USB82/162 is a powerful microcontroller that provides a highly flexible and cost
effective solution to many embedded control applications.
The AT90USB82/162 AVR is supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emula-
tors, and evaluation kits.
2.2 Pin Descriptions
2.2.1 VCC
Digital supply voltage.
2.2.2 GND
Ground.
2.2.3
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the AT90USB82/162 as listed on
page 74.
7707F–AVR–11/10
5
5 Page 
AT90USB82/162
4.5 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 4-2. AVR CPU General Purpose Working Registers
General
Purpose
Working
Registers
70
R0
R1
R2
…
R13
R14
R15
R16
R17
…
R26
R27
R28
R29
R30
R31
Addr.
0x00
0x01
0x02
0x0D
0x0E
0x0F
0x10
0x11
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
X-register Low Byte
X-register High Byte
Y-register Low Byte
Y-register High Byte
Z-register Low Byte
Z-register High Byte
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 4-2, each register is also assigned a data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically imple-
mented as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
4.5.1
The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These reg-
isters are 16-bit address pointers for indirect addressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in Figure 4-3.
Figure 4-3. The X-, Y-, and Z-registers
X-register
15
7
R27 (0x1B)
XH
07
R26 (0x1A)
XL
0
0
15 YH
YL 0
7707F–AVR–11/10
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT90USB162.PDF ] | |
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