PDF RTL8100BL Data sheet ( Hoja de datos )

Número de pieza	RTL8100BL
Descripción	Fast Ethernet Controller
Fabricantes	Realtek Microelectronics
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No Preview Available ! RTL8100B(L) REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT RTL8100B(L) 1. Features........................................................................ 2 2. General Description .................................................... 3 3. Pin Assignments .......................................................... 4 4. Pin Description ............................................................ 6 4.1 Power Management/Isolation Interface.................. 6 4.2 PCI Interface .......................................................... 6 4.3 EPROM/EEPROM Interface.................................. 8 4.4 Power Pins.............................................................. 8 4.5 LED Interface......................................................... 8 4.6 Attachment Unit Interface ...................................... 9 4.7 Test and Other Pins ................................................ 9 5. Register Descriptions ................................................ 10 5.1 Receive Status Register in Rx packet header ....... 12 5.2 Transmit Status Register....................................... 13 5.3 ERSR: Early Rx Status Register........................... 14 5.4 Command Register ............................................... 14 5.5 Interrupt Mask Register........................................ 15 5.6 Interrupt Status Register....................................... 15 5.7 Transmit Configuration Register.......................... 16 5.8 Receive Configuration Register ........................... 17 5.9 9346CR: 93C46 Command Register .................... 19 5.10 CONFIG 0: Configuration Register 0 ................ 20 5.11 CONFIG 1: Configuration Register 1 ................ 20 5.12 Media Status Register......................................... 21 5.13 CONFIG 3: Configuration Register3 ................. 22 5.14 CONFIG 4: Configuration Register4 ................. 23 5.15 Multiple Interrupt Select Register ...................... 24 5.16 PCI Revision ID ................................................. 24 5.17 Transmit Status of All Descriptors (TSAD) Register .. 25 5.18 Basic Mode Control Register ............................. 25 5.19 Basic Mode Status Register................................ 26 5.20 Auto-Negotiation Advertisement Register ......... 27 5.21 Auto-Negotiation Link Partner Ability Register 28 5.22 Auto-Negotiation Expansion Register................ 28 5.23 Disconnect Counter ............................................ 29 5.24 False Carrier Sense Counter ............................... 29 5.25 NWay Test Register ........................................... 29 5.26 RX_ER Counter ................................................. 29 5.27 CS Configuration Register ................................. 30 5.28 Config5: Configuration Register 5 ..................... 31 6. EEPROM (93C46) Contents .....................................32 6.1 Summary of the RTL8100B(L) EEPROM Registers...34 6.2 Summary of EEPROM Power Management Registers .34 7. PCI Configuration Space Registers..........................35 7.1 PCI Configuration Space Table ............................35 7.2 PCI Configuration Space Functions......................37 7.3 Default Values after Power-on (RSTB asserted) ..40 7.4 PCI Power Management Functions.......................41 7.5 VPD (Vital Product Data) .....................................43 8. Block Diagram ...........................................................44 9. Functional Description ..............................................45 9.1 Transmit operation ................................................45 9.2 Receive operation..................................................45 9.3 Wander Compensation..........................................45 9.4 Signal Detect.........................................................45 9.5 Line Quality Monitor ............................................45 9.6 Clock Recovery Module .......................................45 9.7 Loopback Operation..............................................45 9.8 Tx Encapsulation ..................................................46 9.9 Collision................................................................46 9.10 Rx Decapsulation ................................................46 9.11 Flow Control .......................................................46 9.11.1. Control Frame Transmission .......................46 9.11.2. Control Frame Reception ............................46 9.12 LED Functions ....................................................47 9.12.1 10/100 Mbps Link Monitor ..........................47 9.12.2 LED_RX ......................................................47 9.12.3 LED_TX.......................................................47 9.12.4 LED_TX+LED_RX .....................................48 10. Application Diagram ...............................................48 11. Electrical Characteristics ........................................49 11.1 Temperature Limit Ratings .................................49 11.2 DC Characteristics ..............................................49 11.2.1 Supply voltage..............................................49 11.2.2 Supply voltage..............................................49 11.3 AC Characteristics ..............................................50 11.3.1 PCI Bus Operation Timing...........................50 12. Mechanical Dimensions ...........................................56 12.1 QFP .....................................................................56 12.2 LQFP...................................................................57 2001-11-9 1 Rev.1.41 1 page 63 RTT3 64 LWAKE 65 RTSET 66 GND 67 RXIN- 68 RXIN+ 69 NC 70 AVDD 71 TXD- 72 TXD+ 73 GND 74 ISOLATEB 75 AVDD 76 NC 77 LED2 78 NC 79 LED1 80 LED0 81 INTAB 82 RSTB 83 CLK 84 GNTB 85 REQB 86 AD31 87 AD30 88 GND 89 AD29 90 VDD 91 AD28 92 AD27 93 AD26 94 AD25 95 AD24 96 VDD25 97 VDD 98 CBE3B 99 IDSEL 100 AD23 1 AD22 2 GND 3 AD21 4 AD20 5 AD19 6 VDD 7 NC 8 AD18 9 AD17 10 AD16 11 CBE2B 12 FRAMEB 13 IRDYB RTL8100BL LQFP RTL8100B(L) 62 GND 61 X1 60 X2 59 AVDD 58 AVDD25 57 PMEB 56 GND 55 VCTRL 54 NC 53 NC 52 NC 51 VDD25 50 AUX 49 EECS 48 EESK 47 EEDI 46 EEDO 45 AD0 44 AD1 43 GND 42 AD2 41 AD3 40 NC 39 VDD 38 AD4 37 AD5 36 AD6 35 NC 34 VDD 33 AD7 32 CBE0B 31 GND 30 AD8 29 AD9 28 AD10 27 AD11 26 AD12 25 AD13 24 AD14 23 AD15 22 VDD 21 CBE1B 20 PAR 19 SERRB 18 PERRB 17 STOPB 16 GND 15 DEVSELB 14 TRDYB 2001-11-9 5 Rev.1.41 5 Page RTL8100B(L) 0052h 0053H 0054h-0057h R/W - R /W 0058h 0059h 005Ah 005Bh 005Ch-005Dh 005Eh 005Fh 0060h-0061h 0062h-0063h 0064h-0065h 0066h-0067h 0068h-0069h 006Ah-006Bh 006Ch-006Dh 006Eh-006Fh 0070h-0071h 0072h-0073h 0074h-0075h 0076-0077h 0078h-007Bh 007Ch-007Fh 0080h 0081-0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch–0093h 0094h–009Bh 009Ch–00A3h 00A4h–00ABh 00ACh–00B3h 00B4h–00BBh 00BCh–00C3h 00C4h–00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 2001-11-9 R/W R/W R/W - R/W R - R R/W R R/W R R R R R/W R R/W - R/W R/W R/W - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W CONFIG1 - TimerInt MSR CONFIG3 CONFIG4 - MULINT RERID - TSAD BMCR BMSR ANAR ANLPAR ANER DIS FCSC NWAYTR REC CSCR - PHY1_PARM TW_PARM PHY2_PARM - CRC0 CRC1 CRC2 CRC3 CRC4 CRC5 CRC6 CRC7 Wakeup0 Wakeup1 Wakeup2 Wakeup3 Wakeup4 Wakeup5 Wakeup6 Wakeup7 LSBCRC0 LSBCRC1 LSBCRC2 LSBCRC3 LSBCRC4 LSBCRC5 Configuration Register 1 Reserved Timer Interrupt Register: Once having written a nonzero value to this register, the Timeout bit of the ISR register will be set whenever the TCTR reaches to this value. The Timeout bit will never be set as long as the TimerInt register is zero. Media Status Register Configuration register 3 Configuration register 4 Reserved Multiple Interrupt Select PCI Revision ID = 10h. Reserved Transmit Status of All Descriptors Basic Mode Control Register Basic Mode Status Register Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Register Auto-Negotiation Expansion Register Disconnect Counter False Carrier Sense Counter N-way Test Register RX_ER Counter CS Configuration Register Reserved PHY parameter 1 Twister parameter PHY parameter 2 Reserved Power Management CRC register0 for wakeup frame0 Power Management CRC register1 for wakeup frame1 Power Management CRC register2 for wakeup frame2 Power Management CRC register3 for wakeup frame3 Power Management CRC register4 for wakeup frame4 Power Management CRC register5 for wakeup frame5 Power Management CRC register6 for wakeup frame6 Power Management CRC register7 for wakeup frame7 Power Management wakeup frame0 (64bit) Power Management wakeup frame1 (64bit) Power Management wakeup frame2 (64bit) Power Management wakeup frame3 (64bit) Power Management wakeup frame4 (64bit) Power Management wakeup frame5 (64bit) Power Management wakeup frame6 (64bit) Power Management wakeup frame7 (64bit) LSB of the mask byte of wakeup frame0 within offset 12 to 75 LSB of the mask byte of wakeup frame1 within offset 12 to 75 LSB of the mask byte of wakeup frame2 within offset 12 to 75 LSB of the mask byte of wakeup frame3 within offset 12 to 75 LSB of the mask byte of wakeup frame4 within offset 12 to 75 LSB of the mask byte of wakeup frame5 within offset 12 to 75 11 Rev.1.41 11 Page

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