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PDF HMD1M32M2GL Data sheet ( Hoja de datos )
| Número de pieza | HMD1M32M2GL | |
| Descripción | 4Mbyte(1Mx32) Fast Page Mode | |
| Fabricantes | Hanbit Electronics | |
| Logotipo |  |
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HANBit
HMD1M32M2GL
4Mbyte(1Mx32) Fast Page Mode, 1K Refresh, 72Pin SIMM, 5V
Design
Part No. HMD1M32M2GL
DESCRIPTION
The HMD1M32M2GL is an 1M x 32 bits Dynamic RAM MODULE which is assembled 2 pieces of 1M x 16bit DRAMs in 42 pin
SOJ package on single sides the printed circuit board with decoupling capacitors. The HMD1M32M2GL is optimized for
application to the systems, which are required high density and large capacity such as main memory of the computers and an
image memory systems, and to the others, which are, requested compact size.
The HMD1M32M2GL provides common data and outputs.
www.DataFSeheaetut4rUe.csom
w 72 pins Single In-Line Package
w Fast Page Mode Capability
w Single +5V± 0.5V power supply
w Fast Access Time & Cycle Time
tRAC tCAC tRC tPC
HMD1M32M2G-5 50 15 90 35
HMD1M32M2G-6 60 15 110 40
w Low Power
w /RAS Only Refresh, /CAS before /RAS Refresh,
Hidden Refresh Capability
w All inputs and outputs TTL Compatible
w 1,024 Refresh Cycles/16ms
PIN DESCRIPTION
PIN
A0 – A9
DQ0 –
DQ31
/RAS
/CAS
/OE
FUNCTION
Address Inputs
Data
Input/Output
Row Address
Strobe
Column
Address Strobe
Data Output
Enable
PIN
/WE
Vcc
Vss
NC
FUNCTION
Read/Write
Enable
Power (+5V)
Ground
No
Connection
PIN ASSIGNMENT
PIN SYMBOL PIN
SYMBO
L
PIN
SYMBOL
1
Vss
25 DQ22 49
DQ8
2 DQ0 26 DQ7 50 DQ24
3 DQ16 27 DQ23 51
DQ9
4
DQ1
28
A8
52 DQ25
5 DQ17 29 NC(A10) 53 DQ10
6 DQ2 30 Vcc 54 DQ26
7 DQ18 31 /WE2 55 DQ11
8
DQ3
32
NC
56 DQ27
9 DQ19 33 Vcc 57 DQ12
10 Vcc 34 /RAS 58 DQ28
11 /WEO 35 Vcc 59 /WE3
12 A0 36 NC 60 DQ29
13 A1 37 NC 61 DQ13
14 A2 38 /OE 62 DQ30
15 A3 39 Vss 63 DQ14
16 A4 40 /CAS 64 DQ31
17 A5 41 Vcc 65 DQ15
18 A6 42 NC 66 Vcc
19 A7 43 NC 67 NC
20 DQ4 44 NC 68
NC
21 DQ20 45 A9 69 Vss
22 DQ5 46 NC(A11) 70
NC
23 DQ21 47 /WE1 71
Vss
24 DQ6 48 Vcc 72
Vss
URL:www.hbe.co.kr
REV.1.0 (August.2002)
1 HANBit Electronics Co., Ltd.
1 page  
HANBit
HMD1M32M2GL
tRRH Read Command Hold Time to /RAS
0
0 ns 8
tWCH Write Command Hold Time
10 10 ns
tWP
Write Command Pulse Width
10
10 ns
tRWL Write Command to /RAS Lead Time
13
15 ns
tCWL Write Command to /CAS Lead Time
13
15 ns
tDS Data-in Setup Time
0 0 ns 9
tDH Data-in Hold Time
10 10 ns 9
tREF
twcs
Refresh Period (1024 Cycle)
Write Command Setup Time
16 16 ms
0 0 ms 7
tCWD /CAS to /WE delay time
36 40 ms 7,13
www.DataSheteRtW4UD.com /RAS to /WE delay time
73 85 ns 7
tAWD Column Address to /WE delay time
48
55 ns 7
tCPWD /CAS precharge to /WE delay time
53
60 ns 7
tCSR
/CAS Setup Time
(/CAS-before-/RAS Refresh Cycle)
5
15
5 ns
tCHR
/CAS Hold Time
(/CAS-before-/RAS Refresh Cycle)
10
10 ns 16
tRPC /RAS Precharge to /CAS Hold Time
5
5 ns
tCPA Access Time from /CAS Precharge
30
35 ns
3
tPC Fast Page Mode Cycle Time
35
40 ns
tCP Fast Page Mode /RAS Precharge Time
10
10 ns 12
tRASP Fast Page Mode /CAS Pulse Time
50
200K
60 200K ns
/RAS Hold Time time from /CAS
tRHCP
Precharge
30
35 ns
tOEA /OE Access Time
13
15 ns
3
tOED /OE to data delay
13 15 ns
tOEZ Output buffer turn off delay time from /OE
0
13 0 15 ns
tOEH /OE command hold time
13 15 ns
tRASS /RAS Pulse Width(CBR self refresh)
100
100 us
tPRS /RAS Precharge Time(CBR self refresh)
90
110 ns
tCHS /CAS Hold Time(CBR self refresh)
-50
-50 ns
Note: 1. An initial pause of 200us is required after power-up followed by any 8 /RAS-only refresh or /CAS-before-/RAS
refresh cycles before proper device operation is achieved.
2. Input voltage levels are VIH / VIL. VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Also, transition times are measured between . VIH and VIL are assumed to be 5ns for all inputs.
3. Measured with a load circuit equivalent to 2TTL loads and 100pF.
4. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only,
if tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC .
5. Assumes that tRCD <= tRCD (max).
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH /
VOL .
7. TWCS, TRWD, TCWD, TCPWD are non restrictive operating parameter. They are included in the data sheet as electrical
characteristics
only. If twcs >= twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance)
throughout
URL:www.hbe.co.kr
REV.1.0 (August.2002)
5 HANBit Electronics Co., Ltd.
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet HMD1M32M2GL.PDF ] | |
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