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PDF AK4220 Data sheet ( Hoja de datos )
| Número de pieza | AK4220 | |
| Descripción | 7:3 Audio Switch and 6:3 Video Switch | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AK4220 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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I [AK4220]
AK4220
7:3 Audio Switch and 6:3 Video Switch
GENERAL DESCRIPTION
The AK4220 is an AV Switch with 7:3 Audio Switches and 6:3 Video Switches. Using CMOS process to
offer the high performance with low power consumption. In the Audio section, on-chip differential input
circuit could separate the external ground noise. The AK4220 integrates a pop noise free circuit for power
on/pff. The AK4220 is offered in a space saving 64-pin LQFP package, ideal for car navigation
applications.
www.DataSheet4U.com
FEATURES
1. Audio Section
• Selector for 7 inputs and 3 outputs
• Differential Input Circuit for Ground Noise Cannel
• THD+N: -92dB (@1Vrms)
• Dynamic Range: 96dB
• Channel-Independent Output Off
• Pop Noise Free Circuit for Power On/Off
• Channel-Independent Input Detection Circuit
2. Video Section
• Selector for 6 inputs and 3 outputs
• Six Composite Signal Inputs
• Video Driver for Composite Signal Output (+6dB)
• Channel-Independent Hi-Z Output
• On-Chip Sync-tip Clamp Circuit
• Frequency Range: 6MHz
• S/N: 74dB
• Input Detection Circuit
3. Control Section
• Serial µP I/F (I2C, 4-wires serial)
• Five Programmable Output pins
4. Power Supply
• Analog: 4.5V ~ 5.5V
• Digital: 3.0V ~ 3.6V
• Low Power Consumption: 186mW
5. Ta = -40 ∼ 85 °C
6. Package: 64pin LQFP
MS0627-E-00
-1-
2007/05
1 page  
I
No. Pin Name
1 RIN+7
2
PDN
3
CAD1
CSN
4
SCL
CCLK
5
SDA
CDTI
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7 INT
8 Q0
9 Q1
10 Q2
11 Q3
12 Q4
13 DVDD
14 DVSS
15 VOUT1
16 VFB1
17 TEST
18 VOUT2
19 VFB2
20 VVDD2
21 VOUT3
22 VFB3
23 VVSS2
24 VIN1
25 VVSS3
26 VIN2
27 VVDD1
28 VIN3
29 VVSS1
30 VIN4
31 IICN
32 VIN5
33 VIN6
34 AVDD
MS0627-E-00
[AK4220]
PIN/FUNCTION
I/O Function
I Rch Audio Positive Input 7
Power down Mode
I
“L”: Power down, Reset
“H”: Power up
The AK4220 should always be reset upon power-up.
I Chip Address1 (IICN pin = “L”)
I Chip Selector (IICN pin = “H”)
I Control Clock Input (IICN pin = “L”)
I Control Clock Input (IICN pin = “H”)
I/O Control Data Input/Output (IICN pin = “L”)
I Control Data Input (IICN pin = “H”)
I Chip Address0 (IICN pin = “L”)
O Control Data Output (IICN pin = “H”)
O Interrupt
O Parallel Output 0 (open drain output)
O Parallel Output 1 (open drain output)
O Parallel Output 2 (open drain output)
O Parallel Output 3 (open drain output)
O Parallel Output 4 (open drain output)
Digital Power Supply
- Normally connected to DVSS with a 0.1μF ceramic capacitor in parallel
with a 10μF electrolytic capacitor.
- Digital Ground
O Video Output 1
I Video Feedback 1
I Test pin, Connected to VVSS.
O Video Output 2
I Video Feedback 2
Video Power Supply, 5V
- Normally connected to VVSS with a 0.1μF ceramic capacitor in parallel
with a 10μF electrolytic capacitor.
O Video Output 3
I Video Feedback 3
- Video Ground2, 0V
I Video Input 1
- Video Ground3, 0V
I Video Input 2
Video Power Supply, 5V
- Normally connected to VVSS with a 0.1μF ceramic capacitor in parallel
with a 10μF electrolytic cap.
I Video Input 3
- Video Ground1, 0V
I Video Input 4
Control Mode Selection
I “L”(Connected to VVSS): IIC Bus
“H” (Connected to VVDD): 4-wire Serial
I Video Input 5
I Video Input 6
Audio Power Supply, 5V
- Normally connected to AVSS with a 0.1μF ceramic capacitor in parallel
with a 10μF electrolytic capacitor.
2007/05
-5-
5 Page 
I
SWITCHING CHARACTERISTICS
(Ta= -40∼85°C; AVDD = VVDD1-2 = 4.5∼5.5V, DVDD= 3.0∼3.6V, CL= 20pF)
Control Interface Timing (I2C Bus, Note: 20)
SCL Clock Frequency
fSCL
-
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first clock pulse) tHD:STA
0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling (Note: 21)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR -
Fall Time of Both SDA and SCL Lines
tF -
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
Capacitive load on bus
www.DaCtaoSnhetreotl4UIn.ctoermface Timing (4-wire serial mode)
Cb
-
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
CDTO Delay
CSN “↑” to CDTO Hi-Z
Power-down & Reset Timing
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
200
80
80
50
50
150
50
50
PDN Pulse Width
(Note: 21)
TPD 150
Note: 20. I2C is a registered trademark of Philips Semiconductors.
Note: 21. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note: 22. The AK4220 should be reset by PDN pin = “L” upon power up.
[AK4220]
400 kHz
- μs
- μs
- μs
- μs
- μs
- μs
- μs
0.3 μs
0.3 μs
- μs
50 ns
400 pF
ns
ns
ns
ns
ns
ns
ns
ns
45 ns
70 ns
ns
MS0627-E-00
- 11 -
2007/05
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AK4220.PDF ] | |
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