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PDF LP2995 Data sheet ( Hoja de datos )

Número de pieza LP2995
Descripción DDR Termination Regulator
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo




1. LP2995






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No Preview Available ! LP2995 Hoja de datos, Descripción, Manual

July 2003
LP2995
DDR Termination Regulator
General Description
The LP2995 linear regulator is designed to meet the JEDEC
SSTL-2 and SSTL-3 specifications for termination of DDR-
SDRAM. The device contains a high-speed operational am-
plifier to provide excellent response to load transients. The
output stage prevents shoot through while delivering 1.5A
continuous current and transient peaks up to 3A in the
application as required for DDR-SDRAM termination. The
LP2995 also incorporates a VSENSE pin to provide superior
load regulation and a VREF output as a reference for the
chipset and DDR DIMMS.
Patents Pending
Features
n Low output voltage offset
n Works with +5v, +3.3v and 2.5v rails
n Source and sink current
n Low external component count
n No external resistors required
n Linear topology
n Available in SO-8, PSOP-8 or LLP-16 packages
n Low cost and easy to use
Applications
n DDR Termination Voltage
n SSTL-2
n SSTL-3
Typical Application Circuit
20039302
© 2003 National Semiconductor Corporation DS200393
www.national.com

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LP2995 pdf
Typical Performance Characteristics (Continued)
VTT vs IOUT
Maximum Output Current (Sourcing) vs VIN
(VDDQ = 2.5)
20039315
Maximum Output Current (Sinking) vs VIN
(VDDQ = 2.5)
20039316
20039317
5 www.national.com

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LP2995 arduino
Physical Dimensions inches (millimeters)
unless otherwise noted
8-Lead Small Outline Package (M8)
NS Package Number M08A
11 www.national.com

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PáginasTotal 13 Páginas
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