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PDF 855PM Data sheet ( Hoja de datos )
| Número de pieza | 855PM | |
| Descripción | Intel 855PM Chipset Memory Controller Hub | |
| Fabricantes | Intel Corporation | |
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Intel® 855PM Chipset Memory
www.DataSheet4U.com Controller Hub (MCH) DDR 200/266
MHz
Datasheet
March 2003
Order Number: 252613-001
1 page  
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www.DataSheet4U.com
3.9.
3.8.5. RID1 – Revision Identification Register – Device #1 ......................................108
3.8.6. SUBC1- Sub-Class Code Register – Device #1.............................................108
3.8.7. BCC1 – Base Class Code Register – Device #1............................................109
3.8.8. MLT1 – Master Latency Timer Register – Device #1 .....................................109
3.8.9. HDR1 – Header Type Register – Device #1...................................................109
3.8.10. PBUSN1 – Primary Bus Number Register – Device #1 .................................110
3.8.11. SBUSN1 – Secondary Bus Number Register – Device #1 ............................110
3.8.12. SUBUSN1 – Subordinate Bus Number Register – Device #1........................110
3.8.13. SMLT1 – Secondary Master Latency Timer Register – Device #1 ................111
3.8.14. IOBASE1 – I/O Base Address Register – Device #1......................................112
3.8.15. IOLIMIT1 – I/O Limit Address Register – Device #1.......................................112
3.8.16. SSTS1 – Secondary PCI-PCI Status Register – Device #1 ...........................113
3.8.17. MBASE1 – Memory Base Address Register – Device #1 ..............................114
3.8.18. MLIMIT1 – Memory Limit Address Register – Device #1 ...............................115
3.8.19. PMBASE1 – Prefetchable Memory Base Address Register – Device #1 ......116
3.8.20. PMLIMIT1 – Prefetchable Memory Limit Address Register – Device #1 .......117
3.8.21. BCTRL1 – PCI-PCI Bridge Control Register – Device #1 ..............................118
3.8.22. ERRCMD1 – Error Command Register – Device #1......................................119
3.8.23. DWTC – DRAM Write Throttling Control Register – Device #1......................120
3.8.24. DRTC – DRAM Read Throttling Control Register – Device #1 ......................122
3.8.25. TSCR – Thermal Sensor Control Register – Device #1 .................................124
3.8.26. TSSR – Thermal Sensor Status Register – Device #1...................................125
3.8.27. THTS – Thermal Sensor High Temperature Setting Register – Device #1....125
3.8.28. TCTS – Thermal Sensor Catastrophic Temperature Setting Register – Device
#1 ...................................................................................................................126
3.8.29. TCOR – Thermal Calibration Offset Register – Device #1 .............................126
3.8.30. TSHTC – Thermal Sensor Hardware Throttling Control Register – Device
#1 ...................................................................................................................127
Power Management Registers – Device #6 ................................................................128
3.9.1. VID6 – Vendor Identification Register – Device #6 ........................................129
3.9.2. DID6 – Device Identification Register – Device #6.........................................130
3.9.3. PCICMD6 – PCI Command Register – Device #6 .........................................130
3.9.4. PCISTS6 – PCI Status Register – Device #6 .................................................131
3.9.5. RID6 – Revision Identification Register – Device #6 ......................................131
3.9.6. SUBC6- Sub-Class Code Register – Device #6.............................................132
3.9.7. BCC6 – Base Class Code Register – Device #6............................................132
3.9.8. HDR6 – Header Type Register – Device #6...................................................132
3.9.9. BAR6 – Base Address Register – Device #6 .................................................133
3.9.10. PMCR – Power Management Control Register – Device #6..........................134
3.9.11. PMCER – Power Management Control Extension Register – Device #6 ......135
4. System Address Map ...............................................................................................................137
4.1. Memory Address Ranges ............................................................................................137
4.1.1. VGA and MDA Memory Space .......................................................................138
4.1.2. PAM Memory Spaces .....................................................................................139
4.1.3. ISA Hole Memory Space ................................................................................140
4.1.4. TSEG SMM Memory Space ...........................................................................140
4.1.5. IOAPIC Memory Space ..................................................................................141
4.1.6. System Bus Interrupt Memory Space .............................................................141
4.1.7. High SMM Memory Space..............................................................................141
4.1.8. AGP Aperture Space (Device #0 BAR) ..........................................................141
4.1.9. AGP Memory and Prefetchable Memory........................................................142
4.1.10. Hub Interface A Subtractive Decode ..............................................................142
4.2. AGP Memory Address Ranges....................................................................................142
Intel® 855PM Chipset Memory Controller Hub (MCH)
DDR 200/266 MHz Datasheet
5
5 Page 
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Intel® 855PM MCH
Product Features
www.DataSheet4U.com
Processor/Host Bus Support
Accelerated Graphics Port (AGP) Interface
Supports the Intel® Pentium® M processor
Supports a single AGP device (either
2x Address, 4x Data
through a connector or on the motherboard)
Supports system bus at 400 MT/s
AGP Support
Supports host bus Dynamic Bus Inversion
Supports AGP 2.0 including 1x, 2x, and 4x
(DBI)
AGP data transfers and 2x/4x Fast Write
Supports 32-bit host bus addressing
protocol
12 deep In-Order Queue
Supports only 1.5-V AGP electricals
AGTL+ bus driver technology with
32 deep AGP request queue
integrated GTL termination resistors and
PCI semantic (FRAME# initiated) accesses
low voltage operation (1.05 V)
to DRAM are snooped
Support for DPWR# signal to Intel®
AGP semantic (PIPE# and SBA) accesses to
Pentium® M processor for PSB power
DRAM are not snooped
management
High priority access support
Memory System
Hierarchical PCI configuration mechanism
Directly supports one DDR channel, 64b
Delayed transaction support for AGP-to-
wide (72b with ECC)
DRAM FRAME# semantic reads that can
Supports 200-MHz and 266-MHz DDR
not be serviced immediately
devices
32-bit upstream address support for inbound
Supports 64-Mb, 128-Mb, 256-Mb, and
AGP and PCI cycles
512-Mb technologies for x16 devices and x8 32-bit downstream address support for
devices.
outbound PCI and Fast Write cycles
All supported devices have four banks
AGP Busy/Stop Protocol
Configurable optional ECC operation
AGP Clamping and Sense Amp Control
(single bit Error Correction and multiple bit Hub Interface to ICH4-M
Error Detection)
266 MB/s point-to-point hub interface to
Supports up to 16 simultaneous open pages
ICH4-M
Supports page sizes of 2 kB, 4 kB, 8 kB,
66-MHz base clock
and 16 kB. Page size is individually
Supports the following traffic types to the
selected for every row.
ICH4-M
Thermal throttling scheme to selectively
throttle reads and/or writes. Throttling can
be triggered by preset read/write bandwidth
limits.
For DDR, Max of two, double-sided SO-
DIMMs (four rows populated) with
unbuffered PC1600/PC2100 DDR (with or
without ECC)
By using stacked 512-Mb technology, the
largest memory capacity possible is 2.0 GB
System Interrupts
Supports 8259 and processor system bus
interrupt delivery mechanism
Supports interrupts signaled as upstream
Memory Writes from AGP/PCI (PCI
semantics only) and hub interface
MSI sent to the CPU through the System
Hub interface-to-AGP memory writes
Hub interface-to-DRAM
CPU-to-hub interface
Messaging
MSI Interrupt messages
Power Management state change
SMI, SCI, and SERR error indication
Power Management
SMRAM space remapping to A0000h (128
kB)
Supports extended SMRAM space above
256 MB, additional 128k/256k/512k/1 MB
TSEG from Top of Memory, cacheable
(cacheability controlled by CPU)
APM Rev 1.2 compliant power management
Suspend to System Memory
Intel® 855PM Chipset Memory Controller Hub (MCH)
DDR 200/266 MHz Datasheet
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 855PM.PDF ] | |
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