PDF ICS8741004 Data sheet ( Hoja de datos )

Número de pieza	ICS8741004
Descripción	DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS JITTER ATTENUATOR
Fabricantes	Integrated Device Technology
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No Preview Available ! www.DataSheet4U.com DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR ICS8741004 General Description The ICS8741004 is a high performance ICS Differential-to-LVDS/0.7V Differential Jitter HiPerClockS™ Attenuator designed for use in PCI Express™ systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS8741004 has 3 PLL bandwidth modes: 200kHz, 600kHz and 2MHz. The 200kHz mode will provide maximum jitter attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. The 600kHz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. The 2MHz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. Because some 2.5Gb serdes have x20 multipliers while others have x25 multipliers, the ICS8741004 can be set for 1:1 mode or 5/4 multiplication mode (i.e. 100MHz input/125MHz output) using the F_SEL pins. The ICS8741004 uses IDT’s 3rd Generation FemtoClock™ PLL technology to achieve the lowest possible phase noise. The device is packaged in a 24 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. PLL Bandwidth BW_SEL 0 = PLL Bandwidth: ~200kHz Float = PLL Bandwidth: ~600kHz (default) 1 = PLL Bandwidth: ~2MHz Features • Two LVDS and two 0.7V differential output pairs Bank A has two LVDS output pairs and Bank B has two 0.7V differential output pairs • One differential clock input pair • CLK, CLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 98MHz - 160MHz • Input frequency range: 98MHz - 128MHz • VCO range: 490MHz - 640MHz • Cycle-to-cycle jitter: 35ps (maximum) • Full 3.3V operating supply • Three bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs • 0°C to 70°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Pin Assignment nQA1 QA1 VDDO QA0 nQA0 MR BW_SEL nc VDDA F_SELA VDD OEA 1 2 3 4 5 6 7 8 9 10 11 12 24 nQB1 23 QB1 22 VDDO 21 QB0 20 nQB0 19 IREF 18 F_SELB 17 OEB 16 GND 15 GND 14 nCLK 13 CLK ICS8741004 24-Lead TSSOP 4.4mm x 7.8mm x 0.925mm package body G Package Top View IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 1 ICS8741004AG REV. ANOVEMBER 1, 2007 1 page ICS8741004 DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR www.DataSheet4U.com Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical OEA, OEB, MR, VIH Input High Voltage F_SELA, F_SELB BW_SEL OEA, OEB, MR, VIL Input Low Voltage F_SELA, F_SELB BW_SEL 2 VDD – 0.3 -0.3 -0.3 VIM Input Mid Voltage BW_SEL VDD/2 – 0.1 F_SELA, F_SELB, IIH Input High Current MR, BW_SEL OEA, OEB VDD = VIN = 3.465V VDD = VIN = 3.465V IIL MR, Input Low Current F_SELA, F_SELB, VDD = 3.465V, VIN = 0V -5 OEA, OEB, BW_SEL VDD = 3.465V, VIN = 0V -150 Maximum VDD + 0.3 VDD + 0.3 0.8 +0.3 VDD/2 + 0.1 150 5 Units V V V V V µA µA µA µA Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum IIH IIL VPP VCMR Input High Current CLK CLK Input Low Current CLK CLK Peak-to-Peak Voltage; NOTE 1 Common Mode Input Voltage; NOTE 1, 2 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 0.15 GND + 0.5 NOTE 1: VIL should not be less than -0.3V NOTE 2: Common mode input voltage is defined as VIH. Typical Maximum 150 5 1.3 VDD – 0.85 Units µA µA µA µA V V Table 4D. LVDS DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum VOD ∆VOD VOS ∆VOS Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change 290 1.2 Typical 390 1.35 Maximum 490 50 1.5 50 Units mV mV V mV IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 5 ICS8741004AG REV. ANOVEMBER 1, 2007 5 Page ICS8741004 DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR www.DataSheet4U.com Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 1.8V Zo = 50Ω Zo = 50Ω LVHSTL IDT HiPerClockS LVHSTL Driver 3.3V R1 R2 50 50 CLK nCLK HiPerClockS Input Figure 3A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver 3.3V LVPECL Zo = 50Ω Zo = 50Ω 3.3V CLK R1 R2 50 50 nCLK HiPerClockS Input R2 50 Figure 3B. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V LVPECL Zo = 50Ω Zo = 50Ω 3.3V R3 R4 125 125 3.3V CLK nCLK HiPerClockS R1 R2 84 84 Input 3.3V LVDS Zo = 50Ω Zo = 50Ω 3.3V CLK R1 100 nCLK Receiver Figure 3C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver 2.5V R3 33 Zo = 50Ω Zo = 50Ω HCSL R4 33 *Optional – R3 and R4 can be 0Ω R1 50 3.3V CLK nCLK HiPerClockS R2 Input 50 Figure 3E. HiPerClockS CLK/nCLK Input Driven by a 3.3V HCSL Driver Figure 3D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver 2.5V SSTL Zo = 60Ω Zo = 60Ω 2.5V R3 R4 120 120 3.3V CLK R1 R2 120 120 nCLK HiPerClockS Figure 3F. HiPerClockS CLK/nCLK Input Driven by a 2.5V SSTL Driver IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 11 ICS8741004AG REV. ANOVEMBER 1, 2007 11 Page

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