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PDF AD5662 Data sheet ( Hoja de datos )
| Número de pieza | AD5662 | |
| Descripción | 2.7 V to 5.5 V 250 uA Rail-to-Rail Output 16-Bit DAC D/A | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD5662 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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Preliminary Technical Data
2.7 V to 5.5 V, 250 µA, Rail-to-Rail Output
www.DataSheet4U.com
16-Bit nanoDACTM D/A in a SOT-23
AD5662
FEATURES
Low power (250 µA @ 5 V) single 16-bit nanoDACTM
True 12-bit accuracy guaranteed
Tiny 8-lead SOT-23/MSOP package
Power-down to 200 nA @ 5 V, 50 nA @ 3 V
Power-on-reset to zero/midscale
2.7 V to 5.5 V power supply
Guaranteed 16-bit monotonic by design
3 power-down functions
Serial interface with Schmitt-triggered inputs
Rail-to-rail operation
SYNC interrupt facility
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5662 parts are a member of the nanoDACTM family of
devices. They are low power, single, 16-bit buffered voltage-out
DACs. All devices operate from a single 2.7 V to 5.5 V, and are
guaranteed monotonic by design.
The AD5662 requires an external reference voltage to set the
output range of the DAC. The part incorporates a power-on-
reset circuit that ensures the DAC output powers up to 0 V
(AD5662x-1) or midscale (AD5662x-2), and remains there until
a valid write takes place. The part contains a power-down
feature that reduces the current consumption of the device to
200 nA at 5 V, and provides software selectable output loads
while in power-down mode.
The low power consumption of this part in normal operation
makes it ideally suited to portable battery-operated equipment.
The power consumption is 0.7 mW at 5 V, reducing to 1 µW in
power-down mode.
The AD5662’s on-chip precision output amplifier allows rail-to-
rail output swing to be achieved. The AD5662 utilizes a versatile
3-wire serial interface that operates at clock rates up to 30 MHz,
and is compatible with standard SPI™, QSPI™, MICROWIRE™,
and DSP interface standards.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
FUNCTIONAL BLOCK DIAGRAM
VREF GND VDD
POWER-ON
RESET
AD5662
DAC
REGISTER
REF(+)
16-BIT
DAC
OUTPUT
BUFFER
VFB
VOUT
INPUT
CONTROL
LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
SYNC SCLK DIN
Figure 1.
The AD5662 is designed with new technology, and is the next
generation to the AD53xx family.
PRODUCT HIGHLIGHTS
1. 16-bit DAC; true 12-bit accuracy guaranteed.
2. Available in 8-lead SOT-23 and 8-lead MSOP package.
3. Power-on-reset to zero or midscale.
4. Low power. Operates with 2.7 V to 5.5 V supply. Typically
consumes 0.35 mW at 3 V and 0.7 mW at 5 V, making it
ideal for battery-powered applications.
5. Power-down capability. When powered down, the DAC
typically consumes 50 nA at 3 V and 200 nA at 5 V.
6. 10 µs settling time.
RELATED DEVICES
Part No.
AD5620/AD5640/AD5660
Description
3 V/5 V 12-/14-/16-bit DAC with
internal ref in Sot-23
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
AD5662www.DataSheet4U.com
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
t11
t2
t3
t4
t5
t6
t7
t8
t9
t10
Limit at TMIN, TMAX
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
50 33
13 13
13 13
00
55
4.5 4.5
00
50 33
13 13
00
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to sclk fall ignore
SCLK falling edge to SYNC fall ignore
1 Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V, and 20 MHz at VDD = 2.7 V to 3.6 V.
SCLK
SYNC
DIN
t10 t1 t9
t8 t4
t3 t2 t7
DB23
t6
t5
DB0
Figure 2. Serial Write Operation
Rev. PrA | Page 5 of 20
5 Page 
Preliminary Technical Data
AD5662www.DataSheet4U.com
Figure 16. Supply Current vs. Logic Input Voltage
Figure 17. Full-Scale Settling Time
Figure 18. Half-Scale Settling Time
Figure 19. Power-On Reset to 0 V
SCLK
2
VOUT
VDD = VREF = 5V
TA = 25°C
EXITS PD TO MIDSCALE
1
CH1 500mV CH2 5.0V
M1.0µs 500MS/s 2.0ns/pt
Figure 20. Exiting Power-Down to Midscale
2.502500
2.502250
2.502000
2.501750
2.501500
2.501250
2.501000
2.500750
2.500500
2.500250
2.500000
2.499750
2.499500
2.499250
2.499000
2.498750
0
VDD = VREF = 5V
TA = 25°C
13nS/SAMPLE NUMBER
1 LSB CHANGE AROUND
MIDSCALE (0x8000 → 0x7FFF)
GLITCH IMPULSE = 2.723nV.s
50 100 150 200 250 300 350 400 450 500 550
SAMPLE NUMBER
Figure 21. Digital-to-Analog Glitch Impulse (Negative)
Rev. PrA | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD5662.PDF ] | |
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