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PDF LTC4358 Data sheet ( Hoja de datos )

Número de pieza LTC4358
Descripción 5A Ideal Diode
Fabricantes Linear Technology 
Logotipo Linear Technology Logotipo



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No Preview Available ! LTC4358 Hoja de datos, Descripción, Manual

FEATURES
n Replaces a Power Schottky Diode
n Internal 20mΩ N-Channel MOSFET
n 0.5μs Turn-Off Time Limits Peak Fault Current
n Operating Voltage Range: 9V to 26.5V
n Smooth Switchover without Oscillation
n No Reverse DC Current
n Available in 14-Pin (4mm × 3mm) DFN and
16-Lead TSSOP Packages
APPLICATIONS
n N+1 Redundant Power Supplies
n High Availability Systems
n Telecom Infrastructure
n Automotive Systems
LTC4358www.DataSheet4U.com
5A Ideal Diode
DESCRIPTION
The LTC®4358 is a 5A ideal diode that uses an internal
20mΩ N-channel MOSFET to replace a Schottky diode
when used in diode-OR and high current diode applica-
tions. The LTC4358 reduces power consumption, heat
dissipation, and PC board area.
The LTC4358 easily ORs power supplies together to in-
crease total system reliability. In diode-OR applications,
the LTC4358 regulates the forward voltage drop across
the internal MOSFET to ensure smooth current transfer
from one path to the other without oscillation. If the power
source fails or is shorted, a fast turnoff minimizes reverse
current transients.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
12V, 5A Diode-OR
VINA = 12V
IN DRAIN
LTC4358
GND
OUT
VDD
VINB = 12V
IN DRAIN
LTC4358
GND
OUT
VDD
4358 TA01
VOUT TO
5A LOAD
Power Dissipation vs Load Current
3.0
2.5
DIODE (B530C)
2.0
1.5
POWER SAVED
1.0
0.5
0
0
FET (LTC4358)
24
6
CURRENT (A)
8
4358 TA01b
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LTC4358 pdf
LTC4358www.DataSheet4U.com
PIN FUNCTIONS (DE/FE PACKAGES)
DRAIN: The exposed pad is the drain of the internal
N-channel MOSFET. This pin must be connected to OUT
(Pin 9/Pin 10).
GATE: Gate Drive Output. If reverse current flows, a fast
pulldown circuit quickly connects the GATE pin to the IN
pin, turning off the MOSFET. Leave open if unused.
GND: Device Ground.
IN: Input Voltage and Fast Pulldown Return. IN is the
anode of the ideal diode. The voltage sensed at this pin is
used to control the source-drain voltage drop across the
internal MOSFET. If reverse current starts to flow, a fast
pulldown circuit quickly turns off the internal MOSFET. The
fast pulldown current is returned through this pin.
NC: No Connection. Not internally connected.
OUT: Output Voltage. The OUT pin is the cathode of the ideal
diode and the common output when multiple LTC4358s
are configured as an ideal diode-OR. The voltage sensed
at this pin is used to control the source-drain voltage drop
across the MOSFET. Connect this pin to the drain of the
internal N-channel MOSFET (Pin 15/Pin 17).
VDD: Positive Supply Input. The LTC4358 is powered from
the VDD pin. Connect this pin to OUT either directly or
through an RC hold-up circuit.
BLOCK DIAGRAM
IN
DRAIN
GATE
FPD
COMP
25mV +–
CHARGE PUMP
OUT
GATE
AMP
IN
–+ 25mV
VDD
GND
4358 BD
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LTC4358 arduino
PACKAGE DESCRIPTION
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BC
LTC4358www.DataSheet4U.com
3.58
(.141)
4.90 – 5.10*
(.193 – .201)
3.58
(.141)
16 1514 13 12 1110 9
6.60 ±0.10
4.50 ±0.10
SEE NOTE 4
2.94
(.116)
0.45 ±0.05
1.05 ±0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° 8°
2.94
(.116)
6.40
(.252)
BSC
12345678
1.10
(.0433)
MAX
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2.
DIMENSIONS
ARE
IN
MILLIMETERS
(INCHES)
3. DRAWING NOT TO SCALE
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE16 (BC) TSSOP 0204
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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