PDF CY28410-2 Data sheet ( Hoja de datos )

Número de pieza	CY28410-2
Descripción	Clock Generator
Fabricantes	SpectraLinear
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Hay una vista previa y un enlace de descarga de CY28410-2 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas
No Preview Available ! www.DataSheet4U.com CY28410-2 Clock Generator for Intel£ Grantsdale Chipset Features • Compliant with Intel£ CK410 • Supports Intel P4 and Tejas CPU • Selectable CPU frequencies • Differential CPU clock pairs • 100 MHz differential SRC clocks • 96 MHz differential dot clock • 48 MHz USB clocks • 33-MHz PCI clock • Low-voltage frequency select input • I2C support with readback capabilities • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 3.3V power supply • 56-pin SSOP and TSSOP packages CPU x2 / x3 SRC x6 / x7 PCI x9 REF x1 DOT96 x1 USB_48 x1 Block Diagram XIN XOUT FS_[C:A] VTT_PWRGD# IREF XTAL OSC PLL Ref Freq PLL1 Divider Network PD PLL2 SDATA SCLK I2C Logic Pin Configuration VDD_REF REF VDD_PCI VSS_PCI VDD_CPU CPUT[0:1], CPUC[0:1], CPU(T/C)2_ITP] VDD_SRC SRCT[1:6], SRCC[1:6] PCI3 PCI4 PCI5 VSS_PCI VDD_PCI PCIF0/ITP_EN PCIF1 VDD_PCI PCI[0:5] PCIF2 VDD_48 VDD_PCIF USB_48 PCIF[0:2] VSS_48 DOT96T VDD_48 MHz DOT96C FS_B/TEST_MODE DOT96T DOT96C USB_48 VTT_PWRGD#/PD FS_A SRCT1 SRCC1 VDD_SRC SRCT2 SRCC2 SRCT3 SRCC3 SRC4-SATAT SRC4_SATAC VDD_SRC 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 56 SSOP/TSSOP PCI2 PCI1 PCI0 FS_C/TEST_SEL REF VSS_REF XIN XOUT VDD_REF SDATA SCLK VSS_CPU CPUT0 CPUC0 VDD_CPU CPUT1 CPUC1 IREF VSSA VDDA CPUT2_ITP/SRCT7 CPUC2_ITP/SRCC7 VDD_SRC SRCT6 SRCC6 SRCT5 SRCC5 VSS_SRC Rev 1.0, November 20, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 16 www.SpectraLinear.com 1 page CY28410-2www.DataSheet4U.com Byte 1: Control Register 1 Bit @Pup 71 Name PCIF0 61 DOT_96T/C 51 USB_48 41 REF 3 0 CPU PLL Spread Percentage 21 CPU[T/C]1 11 CPU[T/C]0 00 Byte 2: Control Register 2 Bit @Pup 71 CPUT/C SRCT/C PCIF PCI Name PCI5 61 PCI4 51 PCI3 41 PCI2 31 PCI1 21 PCI0 11 PCIF2 01 PCIF1 Byte 3: Control Register 3 Bit @Pup 70 60 50 40 30 Name SRC7 SRC6 SRC5 SRC4 SRC3 Description PCIF0 Output Enable 0 = Disabled, 1 = Enabled DOT_96 MHz Output Enable 0 = Disable (Hi-Z), 1 = Enabled USB_48 MHz Output Enable 0 = Disabled, 1 = Enabled REF Output Enable 0 = Disabled, 1 = Enabled Select CPU PLL Spread Percentage 0: –0.5% Downspread 1:±0.25% Centerspread CPU[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enabled CPU[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enabled Spread Spectrum Enable 0 = Spread off, 1 = Spread on PCI5 Output Enable 0 = Disabled, 1 = Enabled PCI4 Output Enable 0 = Disabled, 1 = Enabled PCI3 Output Enable 0 = Disabled, 1 = Enabled PCI2 Output Enable 0 = Disabled, 1 = Enabled PCI1 Output Enable 0 = Disabled, 1 = Enabled PCI0 Output Enable 0 = Disabled, 1 = Enabled PCIF2 Output Enable 0 = Disabled, 1 = Enabled PCIF1 Output Enable 0 = Disabled, 1 = Enabled Description Description Allow control of SRC[T/C]7 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# Allow control of SRC[T/C]6 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# Allow control of SRC[T/C]5 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# Allow control of SRC[T/C]4 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# Allow control of SRC[T/C]3 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# Rev 1.0, November 20, 2006 Page 5 of 16 5 Page CY28410-2www.DataSheet4U.com Absolute Maximum Conditions Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. DC Electrical Specifications Parameter Description Condition Min. Max. Unit VDD_A, 3.3V Operating Voltage VDD_REF, VDD_PCI, VDD_3V66, VDD_48, VDD_CPU 3.3 ± 5% 3.135 3.465 V VILI2C VIHI2C VIL_FS VIH_FS VILFS_C VIMFS_C VIH FS_C VIL VIH IIL IIH VOL VOH IOZ CIN COUT LIN VXIH VXIL IDD3.3V IPD3.3V IPD3.3V Input Low Voltage SDATA, SCLK Input High Voltage SDATA, SCLK FS_A/FS_B Input Low Voltage FS_A/FS_B Input High Voltage FS_C Low Range FS_C Mid Range FS_C High Range Input Low Voltage Input High Voltage Input Low Leakage Current except internal pull-up resistors, 0 < VIN < VDD Input High Leakage Current except internal pull-down resistors, 0 < VIN < VDD Output Low Voltage IOL = 1 mA Output High Voltage IOH = –1 mA High-impedance Output Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Xin High Voltage Xin Low Voltage Dynamic Supply Current At max load and freq per Figure 7 Power-down Supply Current PD asserted, Outputs driven Power-down Supply Current PD asserted, Outputs Hi-Z – 1.0 2.2 – VSS – 0.3 0.35 0.7 VDD + 0.5 0 0.35 0.7 1.7 2.1 VDD VSS – 0.5 0.8 2.0 VDD + 0.5 –5 5 – 0.4 2.4 – –10 10 25 36 –7 0.7VDD 0 – VDD 0.3VDD 550 – 70 –2 V V V V V V V V V PA PA V V PA pF pF nH V V mA mA mA AC Electrical Specifications Parameter Crystal TDC Description XIN Duty Cycle TPERIOD XIN Period TR / TF TCCJ LACC CPU at 0.7V TDC TPERIOD XIN Rise and Fall Times XIN Cycle to Cycle Jitter Long-term Accuracy CPUT and CPUC Duty Cycle 100-MHz CPUT and CPUC Period Condition Min. Max. Unit The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification When XIN is driven from an external clock source Measured between 0.3VDD and 0.7VDD As an average over 1-Ps duration Over 150 ms 47.5 69.841 – – – 52.5 % 71.0 ns 10.0 ns 500 ps 300 ppm Measured at crossing point VOX Measured at crossing point VOX 43 57 % 9.997001 10.00300 ns Rev 1.0, November 20, 2006 Page 11 of 16 11 Page

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