PDF IDT23S09E Data sheet ( Hoja de datos )

Número de pieza	IDT23S09E
Descripción	3.3V ZERO DELAY CLOCK BUFFER SPREAD SPECTRUM COMPATIBLE
Fabricantes	Integrated Device Technology
Logotipo
Hay una vista previa y un enlace de descarga de IDT23S09E (archivo pdf) en la parte inferior de esta página. Total 8 Páginas
No Preview Available ! IDT23S09E 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAwLwTwE.MDPatEaRSAheTeUtR4UE.cRoAmNGES 3.3V ZERO DELAY IDT23S09E CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE FEATURES: • Phase-Lock Loop Clock Distribution • 10MHz to 200MHz operating frequency • Distributes one clock input to one bank of five and one bank of four outputs • Separate output enable for each output bank • Output Skew < 250ps • Low jitter <200 ps cycle-to-cycle • IDT23S09E-1 for Standard Drive • IDT23S09E-1H for High Drive • No external RC network required • Operates at 3.3V VDD • Spread spectrum compatible • Available in SOIC and TSSOP packages FUNCTIONAL BLOCK DIAGRAM DESCRIPTION: The IDT23S09E is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 200MHz. The IDT23S09E is a 16-pin version of the IDT23S05E. The IDT23S09E accepts one reference input, and drives two banks of four low skew clocks. The -1H version of this device operates up to 200MHz frequency and has higher drive than the -1 device. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the IDT23S09E enters power down. In this mode, the device will draw less than 12µA for Commercial Temperature range and less than 25µA for Industrial temperature range, and the outputs are tri-stated. The IDT23S09E is characterized for both Industrial and Commercial operation. 1 REF PLL 16 CLKOUT 2 CLKA1 3 CLKA2 14 CLKA3 15 CLKA4 S2 8 S1 9 Control Logic The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL c 2003 Integrated Device Technology, Inc. TEMPERATURE 1 RANGES 6 CLKB1 7 CLKB2 10 CLKB3 11 CLKB4 OCTOBER 2003 DSC - 6399/8 1 page IDT23S09E 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAwLwTwE.MDPatEaRSAheTeUtR4UE.cRoAmNGES SWITCHING CHARACTERISTICS (23S09E-1) - INDUSTRIAL(1,2) Symbol Parameter Conditions Min. t1 Output Frequency 10pF Load 10 30pF Load 10 Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 40 t3 Rise Time Measured between 0.8V and 2V — t4 Fall Time Measured between 0.8V and 2V — t5 Output to Output Skew All outputs equally loaded — t6A Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — t6B Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 in PLL bypass mode (IDT23S09E only) 1 t7 Device-to-Device Skew Measured at VDD/2 on the CLKOUT pins of devices — tJ Cycle-to-Cycle Jitter Measured at 66.66MHz, loaded outputs — tLOCK PLL Lock Time Stable power supply, valid clock presented on REF pin — NOTES: 1. REF Input has a threshold voltage of VDD/2. 2. All parameters specified with loaded outputs. Typ. Max. Unit — 200 MHz — 100 50 60 % — 2.5 ns — 2.5 ns — 250 ps 0 ±350 ps 5 8.7 ns 0 700 ps — 200 ps — 1 ms SWITCHING CHARACTERISTICS (23S09E-1H) - INDUSTRIAL(1,2) Symbol Parameter Conditions Min. Typ. Max. Unit t1 Output Frequency 10pF Load 30pF Load 10 — 200 MHz 10 — 100 Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 40 50 60 % Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT <50MHz 45 50 55 % t3 Rise Time Measured between 0.8V and 2V — — 1.5 ns t4 Fall Time Measured between 0.8V and 2V — — 1.5 ns t5 Output to Output Skew All outputs equally loaded — — 250 ps t6A Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — t6B Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 in PLL bypass mode (IDT23S09E only) 1 0 ±350 ps 5 8.7 ns t7 Device-to-Device Skew Measured at VDD/2 on the CLKOUT pins of devices — 0 700 ps t8 Output Slew Rate Measured between 0.8V and 2V using Test Circuit 2 1 — — V/ns tJ Cycle-to-Cycle Jitter Measured at 66.66MHz, loaded outputs — — 200 ps tLOCK PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms NOTES: 1. REF Input has a threshold voltage of VDD/2. 2. All parameters specified with loaded outputs. 5 5 Page

Páginas	Total 8 Páginas
PDF Descargar	[ Datasheet IDT23S09E.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
IDT23S09	IDT23S09 3.3V ZERO DELAY CLOCK BUFFER / SPREAD SPECTRUM COMPATIBLE	Integrated Device
IDT23S09-1DC	IDT23S09 3.3V ZERO DELAY CLOCK BUFFER / SPREAD SPECTRUM COMPATIBLE	Integrated Device
IDT23S09-1DCI	IDT23S09 3.3V ZERO DELAY CLOCK BUFFER / SPREAD SPECTRUM COMPATIBLE	Integrated Device
IDT23S09-1HDC	IDT23S09 3.3V ZERO DELAY CLOCK BUFFER / SPREAD SPECTRUM COMPATIBLE	Integrated Device

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar