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PDF MAX1961 Data sheet ( Hoja de datos )
| Número de pieza | MAX1961 | |
| Descripción | 1MHz PWM Step-Down Controllers | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-2740; Rev 0; 1/03
EVAALVUAAILTAIOBNLEKIT
www.DataSheet4U.com
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
General Description
The MAX1960/MAX1961/MAX1962 high-current, high-
efficiency voltage-mode step-down DC-DC controllers
operate from a 2.35V to 5.5V input and generate output
voltages down to 0.8V at up to 20A. An on-chip charge
pump generates a regulated 5V for MOSFET drive.
Additionally, adaptive dead-time drivers allow a
wide variety of MOSFETs to be used without risking
shoot-through.
Fixed-frequency PWM operation and external synchro-
nization make these controllers suitable for telecom
and datacom applications. The operating frequency is
programmable to either 500kHz or 1MHz, or from
450kHz to 1.2MHz with an external clock. A clock output
is provided to synchronize another converter for 180°
out-of-phase operation. A high closed-loop bandwidth
provides excellent transient response for applications
with dynamic loads.
Lossless current sensing in the MAX1960 and
MAX1961 is achieved by monitoring the drain-to-source
voltage of the low-side external FET. The current limit is
scalable to accommodate a wide variety of MOSFETs
and load currents. The MAX1962 has 10% accurate
sense-resistor-based current limiting.
The MAX1960 and MAX1962 have an adjustable output
voltage from 0.8V to 4.95V. The MAX1961 and
MAX1962 have four preset output voltages (1.5V, 1.8V,
2.5V, and 3.3V) and feature 0.5% voltage accuracy
over temperature, line, and load variations. The
MAX1960 and MAX1961 also feature voltage-margining
control inputs that shift the output voltage up or down
by 4% for system testing.
Applications
ASIC, FPGA, DSP, and CPU Core and I/O Voltages
Cellular Base Stations
Telecom and Network Equipment
Server and Storage Systems
Pin Configurations and Selector Guide appear at the end
of the data sheet.
Features
o 0.5% Accurate Output
o Operates from 2.35V to 5.5V Supply
o Generates Low Output Voltage Down to 0.8V
o On-Chip Charge Pump Provides 5V Gate Drive
o Ceramic or Electrolytic Capacitors
o 94% Efficiency
o External Synchronization from 450kHz to 1.2MHz
o 500kHz/1MHz Fixed-Frequency PWM Operation
o Fast Transient Response
o Two Converters Can Operate 180° Out-of-Phase
o ±4% Voltage Margining for System Test
o 10% Accurate Current Sensing (MAX1962)
o Adaptive Dead Time Prevents Shoot-Through
Ordering Information
PART
MAX1960EEP
MAX1961EEP
MAX1962EEP
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
20 QSOP
20 QSOP
20 QSOP
Typical Operating Circuit
INPUT
2.35V TO 5.5V
C+
VCC
C-
AVDD
VOLTAGE
MARGINING
AND ON/OFF
MAX1960
VDD
CTL1
CTL2
COMP
BST
DH
REF LX
DL
GND PGND
OPTIONAL
SYNCHRONIZATION
CLKOUT
180° OUT-OF-PHASE
FSET/SYNC
CLKOUT
ILIM
FB
OUTPUT
0.8 TO 0.87 ✕ VIN
UP TO 20A
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
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2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
ELECTRICAL CHARACTERISTICS (continued)
(VVCC = 3.3V, Circuits of Figures 9–12, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
Current-Limit Threshold (Negative
Direction, Adjustable, VLX - VPGND)
DH Gate-Driver On-Resistance
DL Gate-Driver On-Resistance (Pullup)
DL Gate-Driver On-Resistance (Pulldown)
FSET/SYNC Pulse Width
FSET/SYNC Rise/Fall Time
CTL_, FSET/SYNC, EN Input High Voltage
CTL_, FSET/SYNC, EN Input Low Voltage
CTL_, FSET/SYNC, EN Input Current
CLKOUT VOL
CONDITIONS
MAX1960/MAX1961, RILIM = 160kΩ
RILIM = 400kΩ
VBST - VLX = 5V, pulling up or down
DL high state
DL low state
Minimum high time
Minimum low time
VVCC = 2.35V to 5.5V
VVCC = 2.35V to 5.5V
Sinking 1mA
CLKOUT VOH
Sourcing 1mA
MIN
90
245
200
200
2.0
-1
VVCC -
0.2V
CLKOUT Rise/Fall Time
CLOAD = 100pF
Note 1: Guaranteed by design.
Note 2: Specifications at -40°C are guaranteed by design, and not production tested.
TYP
MAX
125
296
3.5
3.5
1.6
100
0.8
+1
0.1
40
UNITS
mV
Ω
Ω
Ω
ns
ns
V
V
µA
V
V
ns
_______________________________________________________________________________________ 5
5 Page 
www.DataSheet4U.com
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
ILIM
(MAX1960/MAX1961)
CLKOUT
FSET/SYNC
OUT
OSC
OSC
COMP
CURRENT
SENSE
UVLO
LX
PGND
S
COMP
R
Q
VDD
Q
OUT
(MAX1961/MAX1962)
FB
(MAX1960/MAX1962)
VSEL
(MAX1961/MAX1962)
CTL1
(MAX1960/MAX1961)
CTL2
(MAX1960/MAX1961)
EN
(MAX1962)
FEEDBACK
SELECT
SHUTDOWN
AND VOLTAGE
MARGINING
ERROR
AMP
SOFT-START
DAC
MAX1960/
MAX1961/
MAX1962
OSC
REF
CHARGE
PUMP
CS
(MAX1962)
BST
DH
LX
DL
PGND
AVDD
REF
VDD
C+
C-
VCC
GND
Figure 1. Functional Diagram
MOSFET Gate Drivers
The DH and DL drivers are designed to drive logic-level
N-channel MOSFETs to optimize system cost and effi-
ciency. MOSFETs with RDSON rated at VGS 4.5V are
recommended. An adaptive dead-time circuit monitors
the DL output and prevents the high-side MOSFET from
turning on until DL is fully off. There must be a low-resis-
tance, low-inductance path from the DL driver to the
MOSFET gate for the adaptive dead-time circuit to work
properly. Otherwise, the internal sense circuitry could
interpret the MOSFET gate as “off” while there is actually
still charge left on the gate. Use very short, wide traces
measuring no more than 20 squares (50mils to 100mils
wide if the MOSFET is 1in from the IC).
Undervoltage Lockout and Soft-Start
There are two undervoltage lockout (UVLO) circuits on
the MAX1960/MAX1961/MAX1962. The first UVLO cir-
cuit monitors VCC, which must be above 2.15V (typ) in
order for the charge pump to operate. The second
UVLO circuit monitors the output of the charge pump.
The charge-pump output, VDD, must be above 4.2V
(typ) in order for the PWM converter to operate. Both
UVLO circuits inhibit switching and force DL high and DH
low when either VCC or VDD are below their threshold.
When the monitored voltages are above their thresh-
olds, an internal soft-start timer ramps up the error-
amplifier reference voltage. The ramp occurs in eighty
10mV steps. Full output voltage is reached 1.28ms after
activation with a 1MHz operating frequency.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet MAX1961.PDF ] | |
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