CY14B101Q2 Datasheet PDF - Cypress Semiconductor
| Part Number | CY14B101Q2 | |
| Description | 1 Mbit (128K x 8) Serial SPI nvSRAM | |
| Manufacturers | Cypress Semiconductor | |
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CY14B101Q1
CY14B101Q2
www.DataSheet4U.com
CY14B101Q3
1 Mbit (128K x 8) Serial SPI nvSRAM
Features
■ 1 Mbit Nonvolatile SRAM
❐ Internally organized as 128K x 8
❐ STORE to QuantumTrap Nonvolatile Elements initiated au-
tomatically on Power Down (AutoStore) or by user using HSB
Pin (Hardware Store) or SPI instruction (Software Store)
❐ RECALL to SRAM initiated on Power Up (Power Up Recall)
or by SPI Instruction (Software RECALL)
❐ Automatic STORE on Power Down with a small Capacitor
■ High Reliability
❐ Infinite Read, Write, and RECALL Cycles
❐ 1 Million STORE cycles to QuantumTrap
❐ Data Retention: 20 Years
■ High Speed Serial Peripheral Interface (SPI)
❐ 40 MHz Clock Rate
❐ Supports SPI Modes 0 (0,0) and 3 (1,1)
■ Write Protection
❐ Hardware Protection using Write Protect (WP) Pin
❐ Software Protection using Write Disable Instruction
❐ Software Block Protection for 1/4,1/2, or entire Array
■ Low Power Consumption
❐ Single 3V +20%, –10% Operation
❐ Average VCC current of 10 mA at 40 MHz Operation
■ Industry Standard Configurations
❐ Industrial Temperature
❐ CY14B101Q1 has identical pin configuration to industry stan-
dard 8-pin NV Memory
❐ 8-pin DFN and 16-pin SOIC Packages
❐ RoHS Compliant
Logic Block Diagram
Functional Overview
The Cypress CY14B101Q1/CY14B101Q2/CY14B101Q3
combines a 1 Mbit nonvolatile static RAM with a nonvolatile
element in each memory cell. The memory is organized as 128K
words of 8 bits each. The embedded nonvolatile elements incor-
porate the QuantumTrap technology, creating the world’s most
reliable nonvolatile memory. The SRAM provides infinite read
and write cycles, while the QuantumTrap cell provides highly
reliable nonvolatile storage of data. Data transfers from SRAM to
the nonvolatile elements (STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM from the nonvolatile memory (RECALL operation).
Both STORE and RECALL operations can also be triggered by
the user.
Configuration
Feature
AutoStore
Software
STORE
Hardware
STORE
CY14B101Q1
No
Yes
CY14B101Q2
Yes
Yes
CY14B101Q3
Yes
Yes
No No Yes
VCC
VCAP
CS
WP
SCK
HOLD
SI
Instruction decode
Write protect
Control logic
Quantum Trap
128K X 8
SRAM ARRAY
128K X 8
STORE
RECALL
Instruction
register
Address
Decoder
A0-A16
D0-D7
Data I/O register
Power Control
STORE/RECALL
Control
HSB
SO
Status register
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-50091 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 04, 2010
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CY14B101Q1
CY14B101Q2
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AutoStore Operation
The AutoStore operation is a unique feature of nvSRAM which
automatically stores the SRAM data to QuantumTrap during
power down. This Store mechanism is implemented using a
capacitor (VCAP) and enables the device to safely STORE the
data in the nonvolatile memory when power goes down.
During normal operation, the device draws current from VCC to
charge the capacitor connected to the VCAP pin. When the
voltage on the VCC pin drops below VSWITCH during power down,
the device inhibits all memory accesses to nvSRAM and
automatically performs a conditional STORE operation using the
charge from the VCAP capacitor. The AutoStore operation is not
initiated if no write cycle has been performed since last RECALL.
Note If a capacitor is not connected to VCAP pin, Autostore must
be disabled by issuing the AutoStore Disable instruction
specified in AutoStore Disable (ASDISB) on page 13. If
AutoStore is enabled without a capacitor on VCAP pin, the device
attempts an AutoStore operation without sufficient charge to
complete the Store. This may corrupt the data stored in nvSRAM
and Status register. In such case, WRSR instruction needs to be
issued to update the nonvolatile bits BP0, BP1, WPEN to resume
normal functionality.
During power down, the memory accesses are inhibited after the
voltage on VCC pin drops below VSWITCH. To avoid inadvertent
writes, it must be ensured that CS is not left floating prior to this
event. Therefore, during power down the device must be
deselected and CS must be allowed to follow VCC.
Figure 3 shows the proper connection of the storage capacitor
(VCAP) for AutoStore operation. Refer to DC Electrical Charac-
teristics on page 14 for the size of the VCAP.
Note CY14B101Q1 does not support AutoStore operation. The
user must perform Software STORE operation by using the SPI
STORE instruction to secure the data.
Software Store Operation
Software STORE enables the user to trigger a STORE operation
through a special SPI instruction. This operation is initiated
irrespective of whether a write has been performed since last nv
operation.
A STORE cycle takes tSTORE to complete, during which all the
memory accesses to nvSRAM are inhibited. The RDY bit of the
Status register or the HSB pin may be polled to find the Ready
or Busy status of the nvSRAM. After the tSTORE cycle time is
completed, the SRAM is activated again for read and write
operations.
Hardware STORE and HSB pin Operation
The HSB pin in CY14B101Q3 is used to control and
acknowledge STORE operations. If no STORE or RECALL is in
progress, this pin can be used to request a Hardware STORE
cycle. When the HSB pin is driven LOW, nvSRAM conditionally
initiates a STORE operation after tDELAY duration. An actual
STORE cycle starts only if a write to the SRAM has been
performed since the last STORE or RECALL cycle. Reads and
Writes to the memory are inhibited for tSTORE duration or as long
as HSB pin is LOW.
The HSB pin also acts as an open drain driver that is internally
driven LOW to indicate a busy condition, when a STORE cycle
(initiated by any means) or Power up RECALL is in progress.
Upon completion of the STORE operation, the nvSRAM remains
disabled until the HSB pin returns HIGH. Leave the HSB pin
unconnected if not used.
Note CY14B101Q1/CY14B101Q2 do not have HSB pin. RDY bit
of the SPI status register may be probed to determine the Ready
or Busy status of nvSRAM
Figure 3. AutoStore Mode
VCC
0.1uF
VCC
CS VCAP
VSS
VCAP
RECALL Operation
A RECALL operation transfers the data stored in the nonvolatile
Quantum Trap elements to the SRAM. A RECALL may be
initiated in two ways: Hardware RECALL, initiated on power up;
and Software RECALL, initiated by a SPI RECALL instruction.
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared. Next, the nonvolatile information is transferred
into the SRAM cells. All memory accesses are inhibited while a
RECALL cycle is in progress. The RECALL operation does not
alter the data in the nonvolatile elements.
Hardware Recall (Power Up)
During power up, when VCC crosses VSWITCH, an automatic
RECALL sequence is initiated which transfers the content of
nonvolatile memory on to the SRAM. The data would previously
have been stored on the nonvolatile memory through a STORE
sequence.
A Power Up Recall cycle takes tFA time to complete and the
memory access is disabled during this time. HSB pin can be
used to detect the Ready status of the device. user
Software RECALL
Software RECALL enables the user to initiate a RECALL
operation to restore the content of nonvolatile memory on to the
SRAM. A Software RECALL is issued by using the SPI
instruction for RECALL.
A Software RECALL takes tRECALL to complete during which all
memory accesses to nvSRAM are inhibited. The controller must
provide sufficient delay for the RECALL operation to complete
before issuing any memory access instructions.
Document #: 001-50091 Rev. *D
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