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PDF CY8C28243 Data sheet ( Hoja de datos )
| Número de pieza | CY8C28243 | |
| Descripción | (CY8C28xxx) PSoC Programmable System-on-Chip | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY8C28243, CY8C28403, CY8C28413
PRELIMINARY CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
PSoC® Programmable System-on-Chip
Features
■ Varied Resource Options Within One PSoC Device Group
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds up to 24 MHz
❐ 8x8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ 3.0V to 5.25V Operating Voltage
❐ Operating Voltages Down to 1.0V Using On-Chip Switched
Mode Pump (SMP)
❐ Industrial Temperature Range: -40°C to +85°C
■ Advanced Reconfigurable Peripherals (PSoC Blocks)
❐ Up to 12 Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
• Multiple ADC configurations
• Dedicated SAR ADC, up to 118 ksps with Sample and Hold
• Up to 4 Synchronized or Independent Delta-Sigma ADCs
for Advanced Applications
❐ Up to 4 Limited Type E Analog Blocks Provide:
• Dual Channel Capacitive Sensing Capability
• Comparators with Programmable DAC Reference
• Up to 10-bit Single-Slope ADCs
❐ Up to 12 Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• Shift Register, CRC, and PRS Modules
• Up to 3 Full-Duplex UARTs
www.Dat•aSUhpeetot4U6.cHoamlf-Duplex UARTs
• Multiple Variable Data Length SPI™ Masters or Slaves
• Connectable to All GPIO
❐ Complex Peripherals by Combining Blocks
■ Precision, Programmable Clocking
❐ Internal ±2.5% 24/48 MHz Main Oscillator
❐ Optional 32.768 kHz Crystal for Precise On-Chip Clocks
❐ Optional External Oscillator, up to 24 MHz
❐ Internal Low Speed, Low Power Oscillator for Watchdog and
Sleep Functionality
■ Flexible On-Chip Memory
❐ 16K Bytes Flash Program Storage 50,000 Erase/Write Cy-
cles
❐ 1K Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP™)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■ Programmable Pin Configurations
❐ 25 mA Sink, 10 mA Drive on All GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
❐ Analog Input on All GPIO
❐ 30 mA Analog Outputs on GPIO
❐ Configurable Interrupt on all GPIO
■ Additional System Resources
❐ Up to 2 Hardware I2C Resources
• Each Resource Implements Slave, Master, or Multi-Master
Modes
• Operation Between 0 and 400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Flexible Internal Voltage References
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
■ Complete Development Tools
❐ Free Development Software (PSoC Designer™)
❐ Full Featured In-Circuit Emulator, and Programmer
❐ Full Speed Emulation
❐ Flexible and Functional Breakpoint Structure
❐ 128K Trace Memory
System Block Diagram
PSoC
CORE
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
Analog
Drivers
System Bus
Global Digital Interconnect
Global Analog Interconnect
SRAM
1K
SROM Flash 16K
Interrupt
Controller
CPU Core (M8C)
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Block
Array
ANALOG SYSTEM
Analog
Block
Array
Analog
Ref.
Analog
Input
Muxing
Digital
Clocks
2
MACs
4 Type 2 2 I2C POR and LVD
Decimators Blocks System Resets
Internal
Voltage
Ref.
SYSTEM RESOURCES
Switch
Mode
Pump
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-48111 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 26, 2009
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PRELIMINARY
CY8C28xxx
Figure 5. Analog System Block Diagram for CY8C28x23
Devices
P0[7]
P0[5]
P0[3]
P0[1]
P2[3]
P2[1]
P0[6]
P0[4]
P0[2]
P0[0]
P2[6]
P2[4]
Array Input
Configuration
ACI0[1:0]
ACI1[1:0]
Block Array
ACC00
ACC01
ASC10
ASD11
ASD20
ASC21
Interface to
Digital System
www.DataSheet4U.com
RefHi
RefLo
AGND
Analog Reference
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Figure 6. Analog System Block Diagram for CY8C28x13
Devices
All GPIO
P0[7]
P0[5]
P0[3]
P0[1]
P0[6]
P0[4]
P0[2]
P0[0]
Array Input
Configuration
ACI0[1:0]
ACI1[1:0]
Block Array
ACE00
ACE01
ASE10
ASE11
Interface to
Digital System
RefHi
RefLo
AGND
Analog Reference
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-48111 Rev. *C
Page 5 of 63
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PRELIMINARY
CY8C28xxx
28-Pin Part Pinout
Table 4. 28-Pin Part Pinout (SSOP)
Pin Type
Pin
No. Digital Analog Name
Description
CY8C28403, CY8C28413, CY8C28433, CY8C28445, and
CY8C28452 28-Pin PSoC Devices
1 IO I, M, S P0[7] Analog column mux and SAR ADC
input.[6]
S, AI, M, P0[7] 1
28
2 IO IO, M, S P0[5] Analog column mux and SAR ADC input.
Analog column output.[6, 7]
S, AIO, M, P0[5]
S, AIO, M, P0[3]
2
3
27
26
3 IO IO, M, S P0[3] Analog column mux and SAR ADC input.
Analog column output.[6, 7]
S, AI, M, P0[1]
M, P2[7]
4
5
25
24
4 IO I, M, S P0[1] iAnnpaulto.[g6]column mux and SAR ADC
5 IO
M P2[7]
6 IO
7 IO
8 IO
M P2[5]
I, M P2[3] Direct switched capacitor block input.[10]
I, M P2[1] Direct switched capacitor block input.[10]
M, P2[5] 6
23
AI, M, P2[3] 7 SSOP 22
AI, M, P2[1] 8
21
SMP 9
20
I2C0 SCL, M, P1[7] 10
19
I2C0 SDA, M, P1[5] 11
18
M, P1[3] 12
17
9 Output SMP Switch Mode Pump (SMP) connection to I2C0 SCL, XTALin, M, P1[1] 13
external components.
Vss 14
16
15
10 IO
M P1[7] I2C0 Serial Clock (SCL).
11 IO
M P1[5] I2C0 Serial Data (SDA).
12 IO
M P1[3]
13 IO
M
P1[1]
Crystal
(SCL),
IISnpSuPt-(SXCTLAKL[i5n]).,
I2C0
Serial
Clock
14 Power
Vss Ground connection.
15 IO
16 IO
M P1[0] DCarytasta(Sl ODAut)p, uISt S(XPT-ASLDoAuTtA),[5I2].C0 Serial
M P1[2] I2C1 Serial Data (SDA).[8]
17 IO
18 IO
M P1[4] Optional External Clock Input (EXTCLK).
M P1[6] I2C1 Serial Clock (SCL).[8]
19 Input
20 IO
I, M
21 IO
I, M
www.D2a2taSheeIOt4U.com M
XRES
P2[0]
P2[2]
P2[4]
Active high external reset with internal
pull down.
Direct switched capacitor block input.[11]
Direct switched capacitor block input.[11]
External Analog Ground (AGND).
23 IO
M P2[6] External Voltage Reference (VRef).
24 IO I, M, S P0[0] Analog column mux and SAR ADC
input.[6]
25 IO IO, M, S P0[2] Analog column mux and SAR ADC input.
Analog column output.[6, 9]
26 IO IO, M, S P0[4] Analog column mux and SAR ADC input.
Analog column output.[6, 9]
27 IO I, M, S P0[6] Analog column mux and SAR ADC
input.[6]
28 Power
Vdd Supply voltage.
LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input
Vdd
P0[6], M, AI, S
P0[4], M, AIO, S
P0[2], M, AIO, S
P0[0], M, AI, S
P2[6], M, External VRef
P2[4], M, External AGND
P2[2], M, AI
P2[0], M, AI
XRES
P1[6], M, I2C1 SCL
P1[4], M, EXTCLK
P1[2], M, I2C1 SDA
P1[0], M, XTALout, I2C0 SDA
Notes
10. This pin is not a direct switched capacitor block analog input for CY8C28x03 and CY8C28x13 devices.
11. This pin is not a direct switched capacitor block analog input for CY8C28x03, CY8C28x13, CY8C28x23, and CY8C28x33 devices.
Document Number: 001-48111 Rev. *C
Page 11 of 63
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| PDF Descargar | [ Datasheet CY8C28243.PDF ] | |
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