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PDF MFRC522 Data sheet ( Hoja de datos )
| Número de pieza | MFRC522 | |
| Descripción | Standard performance MIFARE and NTAG frontend | |
| Fabricantes | NXP Semiconductors | |
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MFRC522
Standard performance MIFARE and NTAG frontend
Rev. 3.9 — 27 April 2016
112139
Product data sheet
COMPANY PUBLIC
1. Introduction
This document describes the functionality and electrical specifications of the contactless
reader/writer MFRC522.
Remark: The MFRC522 supports all variants of the MIFARE Mini, MIFARE 1K,
MIFARE 4K, MIFARE Ultralight, MIFARE DESFire EV1 and MIFARE Plus RF
identification protocols. To aid readability throughout this data sheet, the MIFARE Mini,
MIFARE 1K, MIFARE 4K, MIFARE Ultralight, MIFARE DESFire EV1 and MIFARE Plus
products and protocols have the generic name MIFARE.
1.1 Differences between version 1.0 and 2.0
The MFRC522 is available in two versions:
• MFRC52201HN1, hereafter referred to version 1.0 and
• MFRC52202HN1, hereafter referred to version 2.0.
The MFRC522 version 2.0 is fully compatible to version 1.0 and offers in addition the
following features and improvements:
• Increased stability of the reader IC in rough conditions
• An additional timer prescaler, see Section 8.5.
• A corrected CRC handling when RX Multiple is set to 1
This data sheet version covers both versions of the MFRC522 and describes the
differences between the versions if applicable.
2. General description
The MFRC522 is a highly integrated reader/writer IC for contactless communication
at 13.56 MHz. The MFRC522 reader supports ISO/IEC 14443 A/MIFARE and NTAG.
The MFRC522’s internal transmitter is able to drive a reader/writer antenna designed to
communicate with ISO/IEC 14443 A/MIFARE cards and transponders without additional
active circuitry. The receiver module provides a robust and efficient implementation for
demodulating and decoding signals from ISO/IEC 14443 A/MIFARE compatible cards and
transponders. The digital module manages the complete ISO/IEC 14443 A framing and
error detection (parity and CRC) functionality.
The MFRC522 supports MF1xxS20, MF1xxS70 and MF1xxS50 products. The MFRC522
supports contactless communication and uses MIFARE higher transfer speeds up to
848 kBd in both directions.
1 page  
NXP Semiconductors
MFRC522
Standard performance MIFARE and NTAG frontend
SDA/NSS/RX EA I2C
24 32 1
D6/ADR_0/
D2/ADR_4 D4/ADR_2 MOSI/MX
D5/ADR_1/ D7/SCL/
D1/ADR_5 D3/ADR_3 SCK/DTRQ MISO/TX
PVDD PVSS
25 26 27 28 29 30 31
25
SPI, UART, I2C-BUS INTERFACE CONTROL
FIFO CONTROL
64-BYTE FIFO
BUFFER
STATE MACHINE
COMMAND REGISTER
CONTROL REGISTER
BANK
PROGRAMABLE TIMER
INTERRUPT CONTROL
VOLTAGE
MONITOR
AND
POWER ON
DETECT
3
DVDD
4
DVSS
15
AVDD
18
AVSS
RESET
CONTROL
POWER-DOWN
CONTROL
6
NRSTPD
23
IRQ
MIFARE CLASSIC UNIT
CRC16
GENERATION AND CHECK
RANDOM NUMBER
GENERATOR
AMPLITUDE
RATING
REFERENCE
VOLTAGE
ANALOG TEST
MULTIPLEXOR
AND
DIGITAL TO
ANALOG
CONVERTER
PARALLEL/SERIAL
CONVERTER
BIT COUNTER
PARITY GENERATION AND CHECK
FRAME GENERATION AND CHECK
BIT DECODING
BIT ENCODING
SERIAL DATA SWITCH
ANALOG TO DIGITAL
CONVERTER
CLOCK
GENERATION,
FILTERING AND
DISTRIBUTION
OSCILLATOR
7
MFIN
8
MFOUT
9 SVDD
21
OSCIN
22
OSCOUT
I-CHANNEL
AMPLIFIER
I-CHANNEL
DEMODULATOR
Q-CHANNEL
AMPLIFIER
Q-CHANNEL
DEMODULATOR
Q-CLOCK
GENERATION
TEMPERATURE
SENSOR
TRANSMITTER CONTROL
16 19 20
17
VMID AUX1 AUX2
RX
Fig 2. Detailed block diagram of the MFRC522
10, 14 11
TVSS TX1
13 12
TX2 TVDD
001aak602
MFRC522
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.9 — 27 April 2016
112139
© NXP Semiconductors N.V. 2016. All rights reserved.
5 of 95
5 Page 
NXP Semiconductors
MFRC522
Standard performance MIFARE and NTAG frontend
8.1.2.2 SPI write data
To write data to the MFRC522 using SPI requires the byte order shown in Table 7. It is
possible to write up to n data bytes by only sending one address byte.
The first send byte defines both the mode and the address byte.
Table 7.
Line
MOSI
MISO
MOSI and MISO byte order
Byte 0
Byte 1
Byte 2
address 0 data 0
data 1
X[1] X[1] X[1]
[1] X = Do not care.
Remark: The MSB must be sent first.
To
...
...
Byte n
data n 1
X[1]
Byte n + 1
data n
X[1]
8.1.2.3 SPI address byte
The address byte must meet the following format.
The MSB of the first byte defines the mode used. To read data from the MFRC522 the
MSB is set to logic 1. To write data to the MFRC522 the MSB must be set to logic 0. Bits 6
to 1 define the address and the LSB is set to logic 0.
Table 8. Address byte 0 register; address MOSI
7 (MSB) 6 5 4 3 2 1 0 (LSB)
1 = read address
0 = write
0
8.1.3 UART interface
8.1.3.1 Connection to a host
MFRC522
RX
RX
TX
TX
DTRQ
MX
DTRQ
MX
001aak587
Fig 8. UART connection to microcontrollers
Remark: Signals DTRQ and MX can be disabled by clearing TestPinEnReg register’s
RS232LineEn bit.
MFRC522
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.9 — 27 April 2016
112139
© NXP Semiconductors N.V. 2016. All rights reserved.
11 of 95
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MFRC522.PDF ] | |
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