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PDF CH375 Data sheet ( Hoja de datos )
| Número de pieza | CH375 | |
| Descripción | USB Bus Interface Chip | |
| Fabricantes | ETC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CH375 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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The DataSheet of CH375 (the first)
1
USB Bus Interface Chip CH375
English DataSheet
Version: 3E
http://wch.cn
1. Introduction
CH375 is a USB bus universal interface chip, supports USB-HOST Mode and USB-DEVICE/SLAVE
Mode. There are 8-bit data bus and read, write, chip select control wire and interrupt output in CH375.It is
convenient to link CH375 to control system bus of MCU/DSP/MPU.CH375 also provides serial
communication in USB-HOST mode. It connects with DSP/MCU/MPU through serial input, output and
interrupt output.
The USB device mode of CH375 is compatible with CH372, and CH375 incorporates all functions of
CH372. For USB-DEVICE/SLAVE mode operation and specification, please refer to the CH372
specification. This data sheet only covers USB-HOST mode operation.
The USB-HOST mode of CH375 supports common USB full-speed devices. Peripheral MCU can
communicate with USB device through CH375 according relevant USB protocol. The CH375 configures
firmware of special communication protocol inside which can deal with Mass-Storage. Peripheral MCU can
read and write general USB store devices (including USB HD, USB flash and USB flash drive) directly
while sector as unit.
The local
controller
MCU
DSP
MCU
MPU
etc
D [7-0]
INT#
CS#
The
interface
chip
CH375
A0
RD#
WR#
D+
D-
Computer or USB
device
such as：
USB printer
USB
keyboard/mouse
USB flash
external HD
USB flash
derive /flash
etc
2. Features
● Full-speed USB-HOST interface, conforms to USB Specification Version 2.0, only needs crystal and
capacitance external.
● Full-speed USB device interface, compatible with CH372, supports exchanging USB-HOST mode and
USB-DEVICE/SLAVE mode dynamically.
● Input and output buffers of host endpoint occupy 64-byte respectively, supports common full-speed USB
device with 12Mbps and low-speed device with 1.5Mbps.
● Supports USB device control transfer, bulk transfer and interrupt transfer.
● Detects USB device plug and unplug automatically and sends message to USB host.
● Configures protocol processor control transfer inside to simplify usual control transfer.
1 page  
The DataSheet of CH375 (the first)
5
CH375.After the reset, the default communication baud-rate of CH375 is 9600bps when it works serial
communication mode. Through the order adjusts serial communication baud-rate dynamically if the MCU
supports upper communication speed. The command needs to input baud-rate detach frequency coefficient
and detach frequency const.
Usually, the active of set baud-rate costs within 1mS,then the CH375 output operation state according
the new-setting communication baud-rate. Consequently, the MCU regulates itself communication baud-rate
after giving the order out.
Many detach frequency coefficient and detach frequency constant corresponding serial communication
baud-rate is given below.
Detach freq coef Detach freq const Serial interface communication baud- rate (bps)
Error
02H B2H
9600
0.16%
02H D9H
19200
0.16%
03H 98H
57600
0.16%
03H CCH
115200
0.16%
03H F3H
460800
0.16%
07H F3H
921600
0.16%
03H C4H
100000
0%
03H FAH
1000000
0%
03H FDH
2000000
0%
02H Const
Formula: 750000/(256-const)
03H Const
Formula: 6000000/(256-const)
5.3. Command ENTER_SLEEP
The order suspends the CH375 and let it enter into low power. The clock of CH375 stops oscillating to
economize power when keeping low power. Once detection the signal of USB bus or MCU writes new
command without input data to CH375 the CH375 can exit the low-power state.
In general, the time to wake up CH375 from low-power state to work normally is several milliseconds.
The CH375 will send USB_INT_WAKE_UP interrupter while totally recovering to work state.
5.4. Command RESET_ALL
The Command of RESET_ALL makes the CH375 reset through hardware. Usually, the hardware reset
finishes within 40mS.
5.5. Command CHECK_EXIST
The Command CHECK_EXIST is used to check the status to examine the CH375.when using the order,
one data at random needs to input .The output data is contrary to the input data if the CH375 is working
normally. For example, the output data is A8H while the input data is 57H.
5.6. Command GET_MAX_LUN
The command can get the max logical unit number of USB storage device. The command needs to
input one data 38H, and the output is the max logical unit number of USB device. Some USB storage
devices support multiple logical unit, add one to the max logical unit number can get the logical unit total.
5.7. Command SET_DISK_LUN
Using this command to set current logical unit number of USB storage device. The data 34H and new
5 Page 
The DataSheet of CH375 (the first)
11
UD+ and UD- are signal bus of USB directly connect to USB bus when works in the USB-DEVICE
mode. They can attach to USB device directly on USB-HOST. The direct or alternating current equal serial
resistance is within 5Ω which protects chip to serial link of insure resistance, inductance or ESD.
The chip CH375 set power-up reset circuit inside, and external supplies reset is not need in generally.
RSTI inputs asynchronous reset signal from outside. The ch375 is reset when RSTI is high-level. When
RSTI recovered to low-level, CH375 will go on time-lapse reset about 20mS and step into work normally. In
order to reduce external disturb and make sure of reset during power-up, capacitance about 0.47uF can attach
between RSTI and VCC. RST and RST# are output reset state pin, act with high-level and low-level
respectively. They output high-level and low-level respectively if CH375 is power-up reset or forced to reset
by outside circuit or reset time-lapse. After reset RST and RST# recovered to low-level and high-level. RST
and RST# offer power-up reset signal to external MCU.
The CH375 needs outside clock of 12MHz to work normally. In common, clock signal is generated by
inverter in CH375 through oscillating of crystal keeping frequency. A crystal of 12MHz between XI and XO,
XI and XO connect a high frequency oscillator capacitance to ground respectively can compose the
peripheral circuit. The 12MHz clock signal directly input to XI while suspending XO.
CH375B supports 3.3V or 5V .The VCC pin inputs external 5V power and V3 pin connects to power
decoupling capacitance with the capacity from 4700pF to 0.02uF when with 5V power. The V3 must attach
to VCC and input external 3.3V power while work power is 3.3V.In addition, the power of other circuit
connection of CH375 is not surpass 3.3V.
6.3. Internal configuration
In the inner of CH375 integrate PLL multiplier, the host and slave USB interface SIE, data buffer,
passive parallel interface, asynchronous serial interface, command explanation device, protocol transaction
device to control transmission, firmware program in common etc.
PLL multiplier takes the 12MHz input from clock and generates a 48MHz reference clock for SIE.
Host-slave USB interface SIE mixes the USB-HOST mode with USB-DEVICE mode. It takes charge
of physical USB data receive and transfer, deals with bit track and synchronization automatically, coding and
decoding of NRZI, bit stuffing, parallel/serial data conversion, CRC data check, transaction handshake, retry
when error, detection USB bus state etc.
Data buffer delays data receive and transfer of USB interface SIE.
Passive parallel interface exchanges data with peripheral MCU/DSP/MUC.
Asynchronous serial interface exchanges data with peripheral MCU/DSP/MUC substance of passive
parallel interface.
Command explanation device analyzes and executes various commands from peripheral
MCU/DSP/MCU.
Protocol transaction device deals controlling transfer at many layers automatically to simplify
peripheral firmware program.
Common firmware program contains two groups. One group used to USB-DEVICE to treat with
numbers of normal affairs in default port 0 of USB automatically. The other used to USB-HOST, handles
with special communication protocol in Mass-Storage automatically.
There are seven endpoints in CH375 inner.
The port0 is a default endpoint, supports up streaming and down streaming. The buffer of upstream and
downstream is 8-byte respectively.
The port1 includes upstream and downstream endpoint and buffer of each is 8-byte. The upstream
endpoint number is 81H while the downstream endpoint number is 01H.
The port2 includes upstream and downstream endpoint and buffer of each is 64-byte. The upstream
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet CH375.PDF ] | |
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