WV3EG64M64ETSU-D3 Datasheet PDF - White Electronic Designs
| Part Number | WV3EG64M64ETSU-D3 | |
| Description | 512MB - 64Mx64 DDR SDRAM UNBUFFERED | |
| Manufacturers | White Electronic Designs | |
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There is a preview and WV3EG64M64ETSU-D3 download ( pdf file ) link at the bottom of this page. Total 10 Pages | ||
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White Electronic Designs
WV3EG64M64ETSU-D3
PRELIMINARY*
512MB – 64Mx64 DDR SDRAM UNBUFFERED
FEATURES
Double-data-rate architecture
PC2700 @ CL 2.5
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh, (8K/64ms refresh)
Serial presence detect with EEPROM
Power supply:
• VCC = VCCQ = +2.5V ±0.2V
184 pin DIMM package
• D3 PCB height: 28.58mm (1.125")
DESCRIPTION
The WV3EG64M64ETSU is a 64Mx64 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of eight 64Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
www.DataSheet4U.com
OPERATING FREQUENCIES
Clock Speed
CL-tRCD-tRP
DDR333 @CL=2.5
166MHz
2.5-3-3
August 2005
Rev. 1
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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White Electronic Designs
WV3EG64M64ETSU-D3
PRELIMINARY
Parameter
Symbol
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCC = VCCQ = 2.5V ± 0.2V
Includes DDR SDRAM component only
Conditions
Operating current
One device bank active; Active-Precharge; tRC = tRC(MIN); tCK = tCK(MIN);
IDD0* DQ, DM and DQS inputs change once per clock cycle; Address and control
inputs change once every two clock cycles
Operating current
IDD1*
One device bank; Active-Read-Precharge; BL = 4; tRC = tRC(MIN); tCK = tCK(MIN);
IOUT = 0mA; Address and control inputs change once per clock cycle
Percharge power-
down standby current
IDD2P**
All device banks are idle; Power-down mode; tCK = tCK(MIN); CKE = LOW
Idle standby current
IDD2F**
CS# = HIGH; All device banks are idle; tCK = tCK(MIN); CKE = HIGH; Address
and other control inputs changing once per clock cycle. VIN = VREF for DQ,
DQS and DM
Active power-down
standby current
IDD3P**
One device bank active; Power-down mode; tCK = tCK(MIN); CKE = LOW
Active standby
current
IDD3N**
CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS(MAX);
tCK = tCK(MIN); DQ, DM and DQS inputs change twice per clock cycle; Address
and other control inputs changing once per clock cycle
Operating current
IDD4R*
Burst = 2; Reads; Continuous burst; One device bank active; Address and
other control inputs changing once per clock cycle; tCK = tCK(MIN); IOUT = 0mA
Operating current
IDD4W*
Burst = 2; Writes; Continuous burst; One device bank active; Address and
other control inputs changing once per clock cycle; tCK = tCK(MIN); DQ, DM and
DQS inputs change twice per clock cycle
Auto refresh current
IDD5**
tRC = tRFC(MIN)
Self refresh current
IDD6**
CKE < 0.2V
wOwrewra.tDinagtcauSrrheentet4U.com IDD7*
Four device bank interleaving Reads Burst = 4 with auto precharge;
tRC = tRFC(MIN); tCK = tCK(MIN); Address and control inputs change only during
Active READ, or WRITE commands
Note: These specifications apply to modules built with Samsung components only.
* Value calculated as one module rank in this operation condition and other module rank in IDD2P (CKE low) mode.
** Value calculated as all module ranks in this operation condition.
DDR333 @
CL = 2.5
1000
1200
40
240
240
400
1440
1480
2000
40
3120
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
August 2005
Rev. 1
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for WV3EG64M64ETSU-D3 electronic component. |
| Information | Total 10 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ WV3EG64M64ETSU-D3.PDF Datasheet ] | |
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Featured Datasheets
| Part Number | Description | Manufacturers |
| WV3EG64M64ETSU-D3 | The function is 512MB - 64Mx64 DDR SDRAM UNBUFFERED. | White Electronic Designs |
| WV3EG64M64ETSU-D4 | The function is 512MB - 64Mx64 DDR SDRAM. | White Electronic Designs |
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