WV3EG265M64EFSU-D4 Datasheet PDF - White Electronic Designs
| Part Number | WV3EG265M64EFSU-D4 | |
| Description | 1GB- 2x64Mx64 DDR SDRAM UNBUFFERED | |
| Manufacturers | White Electronic Designs | |
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White Electronic Designs WV3EG265M64EFSU-D4
1GB – 2x64Mx64 DDR SDRAM UNBUFFERED, w/PLL
FEATURES
Double-data-rate architecture
PC2700 and PC2100
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2, 2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Auto and self refresh, (8K/64ms refresh)
Serial presence detect with EEPROM
Power supply: VCC/VCCQ: 2.5V ± 0.2V
Dual Rank
200 pin SO-DIMM package
• Package height options:
D4: 31.75 mm (1.25”)
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
DESCRIPTION
The WV3EG265M64EFSU is a 2x64Mx64 Double Data
Rate SDRAM memory module based on 512Mb DDR
SDRAM component. The module consists of sixteen
64Mx8 bit with 4 banks DDR SDRAMs in FBGA packages
mounted on a 200 pin substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is subject to change without notice.
www.DataSheet4U.com
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR333 @CL=2.5
166MHz
2.5-3-3
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
October 2005
Rev. 1
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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White Electronic Designs WV3EG265M64EFSU-D4
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°c ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Parameter
Symbol Conditions
DDR333 @ DDR266 @
CL = 2.5
CL = 2
Operating current
One device bank active; Active-Precharge; tRC = tRC(MIN);
IDD0*
tCK = tCK(MIN); DQ, DM and DQS inputs change once per clock
cycle; Address and control inputs change once every two
clock cycles
1360
1240
Operating current
One device bank; Active-Read-Precharge; BL = 4;
IDD1* tRC = tRC(MIN); tCK = tCK(MIN); IOUT = 0mA; Address and control
inputs change once per clock cycle
1600
1480
Percharge power-
down standby current
IDD2P**
All device banks are idle; Power-down mode; tCK = tCK(MIN);
CKE = LOW
360
360
Idle standby current
Active power-down
standby current
IDD2F**
IDD3P**
CS# = HIGH; All device banks are idle; tCK = tCK(MIN);
CKE = HIGH; Address and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS and DM
One device bank active; Power-down mode; tCK = tCK(MIN);
CKE = LOW
1000
840
920
760
Active standby
current
IDD3N**
CS# = HIGH; CKE = HIGH; One device bank active;
tRC = tRAS(MAX); tCK = tCK(MIN); DQ, DM and DQS inputs change
twice per clock cycle; Address and other control inputs
changing once per clock cycle
1080
1000
Operating current
Operating current
IDD4R*
IDD4W*
Burst = 2; Reads; Continuous burst; One device bank active;
Address and other control inputs changing once per clock
cycle; tCK = tCK(MIN); IOUT = 0mA
Burst = 2; Writes; Continuous burst; One device bank active;
Address and other control inputs changing once per clock
cycle; tCK = tCK(MIN); DQ, DM and DQS inputs change twice per
clock cycle
1640
1720
1480
1400
wAwutwo .rDefaretsahSchuerrent4t U.comIDD5**
Self refresh current
IDD6**
Orerating current
IDD7*
tRC = tRFC(MIN)
CKE < 0.2V
Four device bank interleaving Reads Burst = 4 with auto
precharge; tRC = tRFC(MIN); tCK = tCK(MIN); Address and control
inputs change only during Active READ, or WRITE commands
4920
360
3560
4760
360
3120
NOTE:
IDD specification is based on Micron components. Other DRAM Manufacturers specification may be different.
* Value calculated as one module rank in this operating condition and all other module ranks in IDD2P (CKE low) mode.
** Value calculated reflects all module ranks in this operating condition.
DDR266 @
CL = 2.5
1240
1480
360
920
760
1000
1480
1400
4760
360
3120
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
AC OPERATING TEST CONDITIONS
Parameter/Condition
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Differential Voltage, CK and CK# inputs
Input Crossing Point Voltage, CK and CK3 inputs
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
Min
VREF +0.31
0.7
0.5*VCCQ-0.2
Max
VREF -0.31
VCCQ+0.6
0.5*VCCQ+0.2
Unit
V
V
V
V
October 2005
Rev. 1
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for WV3EG265M64EFSU-D4 electronic component. |
| Information | Total 10 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ WV3EG265M64EFSU-D4.PDF Datasheet ] | |
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