WV3EG264M72ESFR-D4 Datasheet PDF - White Electronic Designs
| Part Number | WV3EG264M72ESFR-D4 | |
| Description | 1GB - 2x64Mx72 DDR SDRAM REGISTERED | |
| Manufacturers | White Electronic Designs | |
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White Electronic Designs WV3EG264M72ESFR-D4
ADVANCED*
1GB – 2x64Mx72 DDR SDRAM REGISTERED, w/PLL
FEATURES
200-pin SO-DIMM, dual in-line memory module
Fast data transfer rates: PC2100 and PC2700
Utilizes 266 and 333 Mb/s DDR SDRAM
components
VCC = VCCQ = 2.5V ±0.2V
Bidirectional data strobe (DQS) option
Differential clock inputs (CK and CK#)
DLL to align DQ and DQS transitions with CK
Programmable burst: length (2, 4, 8)
Programmable READ# latency (CL): 2 and 2.5
(clock)
Serial Presence Detect (SPD) with EEPROM
Auto and self refresh: 64ms/ 8,192 cycle refresh
Gold edge contacts
Dual Rank
Package option
• 200 Pin SO-DIMM
• PCB – 31.75mm (1.25") Max
DESCRIPTION
The WV3EG264M72ESFR is a 2x64Mx72 Double Data
Rate DDR SDRAM high density module. This memory
module consists of eighteen 64Mx8 bit with 4 banks DDR
Synchronous DRAMs in FBGA packages, mounted on a
200-pin SO-DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
www.DataSheet4U.com
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR333@CL = 2.5
166MHz
2.5-3-3
DDR266@CL = 2
133MHz
2-2-2
DDR266@CL = 2.5
133MHz
2.5-3-3
August 2005
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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White Electronic Designs WV3EG264M72ESFR-D4
ADVANCED
DDR IDD SPECIFICATIONS AND CONDITIONS
0°C ≤ TCASE < +70°C; VCCQ = +2.5V ± 0.2V, VCC = +2.5V ± 0.2V
Symbol Conditions
335
IDD0 Operating current - One bank Active-Precharge;
1,215
tRC = tRC(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ, DM and DQS
inputs changing twice per clock cycle; address and control inputs changing once per clock cycle
IDD1 Operating current - One bank operation;
One bank open, BL = 4, Reads - Refer to the following page for detailed test condition
IDD2P Percharge power-down standby current;
All banks idle; power - down mode; CKE = <VIL(max); tCK = 100Mhz for DDR200, 133Mhz for
DDR266A & DDR266B; VIN = VREF for DQ, DQS and DM
IDD2F Precharge Floating standby current;
CS# > = VIH(min);All banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for
DDR266A & DDR266B; Address and other control inputs changing once per clock cycle;
VIN = VREF for DQ, DQS and DM
IDD3P Active power - down standby current;
one bank active; power-down mode; CKE = < VIL(max); tCK = 100Mhz for DDR200, 133Mhz for
DDR266A & DDR266B; VIN = VREF for DQ, DQS and DM
IDD3N Active standby current;
CS# > = VIH(min); CKE> = VIH(min); one bank active; active - precharge; tRC = tRASmax; tCK =
100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ, DQS and DM inputs changing
twice per clock cycle; address and other control inputs changing once per clock cycle
1,485
90
810
630
900
IDD4R Operating current - burst read;
Burst length = 2; reads; continguous burst; One bank active; address and control inputs
changing once per clock cycle; CL = 2 at tCK = 100Mhz for DDR200, CL = 2 at tCK = 133Mhz for
DDR266A, CL = 2.5 at tCK = 133Mhz for DDR266B ; 50% of data changing at every burst;
lOUT = 0 m A
IDD4W Operating current - burst write;
Burst length = 2; writes; continuous burst; One bank active address and control inputs
www.DataSDchhDaeRne2gt6i4n6gUAo,.cnCcoLem=pe2r.5claotctkCKcy=cl1e3; 3CMLh=z
2 at tCK = 100Mhz for DDR200, CL = 2 at
for DDR266B ; DQ, DM and DQS inputs
tCK = 133Mhz for
changing twice
per clock cycle, 50% of input data changing at every burst
1.530
1,440
IDD5 Auto refresh current;
tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz;
distributed refresh
5,220
IDD6 Self refresh current;
CKE = < 0.2V; External clock should be on; tCK = 100Mhz for DDR200, 133Mhz for DDR266A
& DDR266B
90
IDD7A Orerating current - Four bank operation;
Four bank interleaving with BL = 4 -Refer to the following page for detailed test condition
3,690
Typical case: VCC = 2.5V, T = 25°C
Worst case: VCC = 2.7V, T = 10°C
Note: IDD specifications are based on Micron components. Other DRAM manufacturers specificaitons may be different.
262
1,215
1,485
90
810
630
900
1.530
1,440
5,220
90
3,645
265
1,080
1,350
90
720
540
810
1,350
1,260
5,040
90
3,195
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
August 2005
Rev. 0
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for WV3EG264M72ESFR-D4 electronic component. |
| Information | Total 11 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ WV3EG264M72ESFR-D4.PDF Datasheet ] | |
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