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AD8120 Datasheet PDF - Analog Devices

Part Number AD8120
Description Triple Skew-Compensating Video Delay Line
Manufacturers Analog Devices 
Logo Analog Devices Logo 



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AD8120 datasheet, circuit
Data Sheet
Triple Skew-Compensating Video Delay
Line with Analog and Digital Control
AD8120
FEATURES
Corrects for unshielded twisted pair (UTP) cable skew
Delay of up to 50 ns per channel
High speed
200 MHz BW @ VOUT = 1.4 V p-p and 0 ns delay
150 MHz BW @ VOUT = 1.4 V p-p and 50 ns delay
Excellent channel-to-channel matching
30 mV offset matching RTI
0.8% gain matching
Low output offset
±30 mV RTI
No external circuitry required to correct for offsets
Independent red, green, and blue delay controls
Drives 4 double-terminated video loads
Digital and analog delay control
6-bit SPI bus
I2C bus
Analog voltage control
Fixed gain of 2
Low noise
High differential input impedance: 500 kΩ
32-lead, 5 mm × 5 mm LFCSP
APPLICATIONS
Keyboard-video-mouse (KVM)
Digital signage
RGB video over UTP cable
Professional video projection and distribution
HD video
Security video
General broadband delay lines
GENERAL DESCRIPTION
The AD8120 is a triple broadband skew-compensating delay line
that corrects for time mismatch between video signals incurred
by transmission in unshielded twisted pairs of Category 5 and
Category 6 type cables. Skew between the individual pairs exists
in most types of multipair UTP cables due to the different twist
rates that are used for each pair to minimize crosstalk between
pairs. For this reason, some pairs are longer than others, and in
long cables, the difference in propagation time between two pairs
can be well into the tens of nanoseconds.
The AD8120 contains three delay paths that provide broadband
delays up to 50 ns, in 0.8 ns increments, using 64 digital control
steps or analog control adjustment. The delay technique used in
the AD8120 minimizes noise and offset at the outputs.
The bandwidth of the AD8120 ranges from 150 MHz to 200 MHz,
depending on the delay setting. This wide bandwidth makes the
AD8120 ideal for use in applications that receive high resolution
video over UTP cables.
The logic circuitry of the AD8120 provides individual delay con-
trols for each channel. The delay times are set independently
using a standard 4-wire SPI bus or a standard I2C bus, or by
applying analog control voltages to the VCR, VCG, and VCB pins.
Analog control offers a simple solution for systems that do not
have digital control available.
The AD8120 is designed to be used with the AD8123 triple
UTP equalizer in video over UTP applications, but it can
also be used in other applications where similar controllable
broadband delays are required.
The AD8120 is available in a 5 mm × 5 mm, 32-lead LFCSP
and is rated to operate over the industrial temperature range
of −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
Rd
Gd
Bd
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009–2012 Analog Devices, Inc. All rights reserved.

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AD8120 equivalent
AD8120
Data Sheet
Parameter
Test Conditions/Comments
Min Typ Max Unit
DIGITAL CONTROL INPUT CHARACTERISTICS SDO/SDA, SCK/SCL, SDI/A1, CS/A0, SER_SEL,
(SEE BELOW FOR POWER DOWN)
MODE
Input Bias Current
2 μA
Input High Voltage
2.6 V
Input Low Voltage
0.6 V
Output High Voltage
4.5 V
Output Low Voltage
0.6 V
POWER DOWN CHARACTERISTICS
PD
Input High Voltage
4.0 V
Input Low Voltage
0.6 V
SPI TIMING CHARACTERISTICS
Clock Frequency
SCK
10 MHz
CS Setup Time, t1
CS to SCK
5 ns
Clock Pulse High, t2
Clock Pulse Low, t3
Data Setup Time, t4
Data Hold Time, t5
SCK
SCK
SDI to SCK
SDI to SCK
50 ns
50 ns
5 ns
5 ns
CS Hold Time, t6
SCK to CS
5 ns
I2C TIMING CHARACTERISTICS
Clock Frequency
SCL
100 kHz
Start Setup Time, t1
Clock Pulse High, t2
SDA to SCL
SCL
10 ns
5 μs
Clock Pulse Low, t3
SCL
5 μs
Data Setup Time, t4
SDA (input) to SCL
100
ns
Data Hold Time, t5
Hold Time, t6
SDA (input) to SCL
SCL to SDA
100
10
ns
ns
POWER SUPPLY
Positive Supply Range
4.5 5.5 V
Negative Supply Range
−5.5 −4.5 V
Positive Quiescent Current
Delay = 0 ns
44 mA
Delay = 50 ns
114 mA
Powered down, PD low
4 mA
Negative Quiescent Current
Delay = 0 ns
37 mA
Delay = 50 ns
108 mA
Powered down, PD low
0.5 mA
Quiescent Current Drift
TMIN to TMAX, delay = 0 ns
0.13 mA/°C
TMIN to TMAX, delay = 50 ns
0.36 mA/°C
+PSRR
RL = 150 Ω, delay = 50 ns
56 dB
−PSRR
RL = 150 Ω, delay = 50 ns
44 dB
Rev. A | Page 4 of 16

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Information Total 17 Pages
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