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PDF ISL6262 Data sheet ( Hoja de datos )
| Número de pieza | ISL6262 | |
| Descripción | Two-Phase Core Regulator | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ISL6262 (archivo pdf) en la parte inferior de esta página. Total 27 Páginas | ||
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®
Data Sheet
May 15, 2006
ISL6262
FN9199.2
Two-Phase Core Regulator for IMVP-6
Mobile CPUs
The ISL6262 is a two-phase buck converter regulator
implementing Intel® IMVP-6 protocol, with embedded gate
drivers. The two-phase buck converter uses two interleaved
channels to effectively double the output voltage ripple
frequency and thereby reduce output voltage ripple
amplitude with fewer components, lower component cost,
reduced power dissipation, and smaller real estate area.
The heart of the ISL6262 is R3 Technology™, Intersil’s
Robust Ripple Regulator modulator. Compared with the
traditional multiphase buck regulator, the R3 Technology™
has the fastest transient response. This is due to the R3
modulator commanding variable switching frequency during
a load transient.
Intel Mobile Voltage Positioning (IMVP) is a smart voltage
regulation technology, which effectively reduces power
dissipation in Intel Pentium processors. To boost battery life,
the ISL6262 supports DPRSLRVR (deeper sleep),
DPRSTP# and PSI# functions and maximizes the efficiency
via automatically enabling different phase operation modes.
At heavy load operation of the active mode, the regulator
commands the two phase continuous conduction mode
(CCM) operation. While the PSI# is asserted at the medium
load in the active mode, the ISL6262 smoothly disables one
phase and operates in a one-phase CCM. When the CPU
enters deeper sleep mode, the ISL6262 enables diode
emulation to maximize the efficiency at the light load.
A 7-bit digital-to-analog converter (DAC) allows dynamic
adjustment of the core output voltage from 0.300V to 1.500V.
A 0.5% system accuracy of the core output voltage over
temperature is achieved by the ISL6262.
A unity-gain differential amplifier is provided for remote CPU
die sensing. This allows the voltage on the CPU die to be
accurately measured and regulated per Intel IMVP-6
specifications. Current sensing can be realized using either
lossless inductor DCR sensing or precision resistor sensing.
A single NTC thermistor network thermally compensates the
gain and the time constant of the DCR variations.
Features
• Precision Two-phase CORE Voltage Regulator
- 0.5% System Accuracy Over Temperature
- Enhanced load line accuracy
• Internal Gate Driver with 2A Driving Capability
• Dynamic Phase Adding/Dropping
• Microprocessor Voltage Identification Input
- 7-Bit VID Input
- 0.300V to 1.500V in 12.5mV Steps
- Support VID Change on-the-fly
• Multiple Current Sensing Schemes Supported
- Lossless Inductor DCR Current Sensing
- Precision Resistive Current Sensing
• Thermal Monitor
• User Programmable Switching Frequency
• Differential Remote CPU Die Voltage Sensing
• Static and Dynamic Current Sharing
• Overvoltage, Undervoltage, and Overcurrent Protection
• Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
PART
NUMBER
PART
TEMP.
MARKING (°C)
PKG.
PACKAGE DWG. #
ISL6262CRZ ISL6262CRZ -10 to 100 48 Ld 7x7 QFN L48.7x7
(Note)
(Pb-free)
ISL6262CRZ-T ISL6262CRZ -10 to 100 48 Ld 7x7 QFN L48.7x7
(Note)
(Pb-free)
ISL6262IRZ ISL6262IRZ -40 to 100 48 Ld 7x7 QFN L48.7x7
(Note)
(Pb-free)
ISL6262IRZ-T ISL6262IRZ -40 to 100 48 Ld 7x7 QFN L48.7x7
(Note)
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
www.DataSheet4U.com
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved. R3 Technology™ is a trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6262
Electrical Specifications VDD = 5V, TA = -40°C to 100°C, Unless Otherwise Specified. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
PGOOD Delay
tpgd TA = -10°C to 100°C
ISL6262CRZ CLK_EN# Low to PGOOD High
5.5
tpgd
ISL6262IRZ
CLK_EN# Low to PGOOD High
5.3
Overvoltage Threshold
Severe Overvoltage Threshold
OCSET Reference Current
OVH
OVHS
VO rising above setpoint > 1ms
VO rising above setpoint > 0.5µs
I(Rbias) = 10µA
160
1.675
9.8
OC Threshold Offset
DROOP rising above OCSET > 120µs
-3.5
Current Imbalance Threshold
Difference between ISEN1 and ISEN2 > 1ms
-
Undervoltage Threshold
(VDIFF-SOFT)
UVf VO falling below setpoint for > 1ms
-365
LOGIC INPUTS
VR_ON, DPRSLPVR and PGD_IN
Input Low
VIL
-
VR_ON, DPRSLPVR and PGD_IN
Input High
VIH
2.3
Leakage Current of VR_ON and
PGD_IN
Leakage Current of DPRSLPVR
DAC(VID0-VID6), PSI# and
DPRSTP# Input Low
IIL
IIH
IIL_DPRSLP
IIH_DPRSLP
VIL
Logic input is low
Logic input is high at 3.3V
DPRSLPVR input is low
DPRSLPVR input is high at 3.3V
-1
-
-1
-
-
DAC(VID0-VID6), PSI# and
DPRSTP# Input High
VIH
0.7
Leakage Current of DAC(VID0-
VID6), PSI# and DPRSTP#
THERMAL MONITOR
IIL Logic input is low
IIH Logic input is high at 1V
-1
-
NTC Source Current
NTC = 1.3 V
53
Over-Temperature Threshold
V(NTC) falling
1.165
VR_TT# Low Output Resistance
CLK_EN# OUTPUT LEVELS
RTT I = 20mA
-
CLK_EN# High Output Voltage
CLK_EN# Low Output Voltage
VOH
VOL
3V3 = 3.3V, I = -4mA
ICLK_EN# = 4mA
2.9
-
TYP
6.8
6.8
200
1.7
10
-
7.5
-300
-
-
0
0
0
0.45
-
-
0
0.45
60
1.18
5
3.1
0.18
MAX
8.1
UNITS
ms
8.1 ms
240
1.725
10.2
3.5
-
-240
mV
V
µA
mV
mV
mV
1V
-V
- µA
1 µA
- µA
1 µA
0.3 V
-V
- µA
1 µA
68
1.205
9
µA
V
Ω
-V
0.4 V
www.DataSheet4U.com
5
FN9199.2
May 15, 2006
5 Page 
ISL6262
Typical Performance Curves 0.36µH Filter Inductor and 4 x 330µF Output SP Caps (Continued)
VOUT
LOAD TRANSIENT
VID3
VOUT
PHASE1,
PHASE2
DYNAMIC VID
ACTIVE MODE
FIGURE 14. LOAD STEP-UP RESPONSE VIA CPU SOCKET
MPGA479, 35A LOAD STEP @ 200A/µs, 2 PHASE
CCM
FIGURE 15. VID3 CHANGE OF 010X000 FROM 1.V TO 1.1V AT
DPRSLPVR = 0, DPRSTP# = 1, PSI# = 1
VOUT
LOAD TRANSIENT
FIGURE 16. LOAD DUMP RESPONSE VIA CPU SOCKET
MPGA479, 35A LOAD STEP @ 200A/µs, 2 PHASE
CCM
VOUT
PHASE1,
PHASE2
VID3
DYNAMIC VID
ACTIVE MODE
FIGURE 17. VID3 CHANGE OF 010X000 FROM 1.1V TO 1V AT
DPRSLPVR = 0, DPRSTP# = 1, PSI# = 1
PSI#
DROP PHASE IN
ACTIVE MODE
VCORE
PHASE1
PSI#
VCORE
ADD PHASE IN
ACTIVE MODE
PHASE1
PHASE2
www.DaFtIaGSUhReeEt41U8..c2o-mCCM TO 1-CCM UPON PSI# ASSERTION WITH
VID LSB CHANGE, AT DPRSLPVR = 0,
DPRSTP# = 1, ILOAD = 10A
11
PHASE2
FIGURE 19. 1-CCM TO 2-CCM UPON PSI# DEASSERTION
WITH VID LSB CHANGE AT DPRSLPVR = 0,
DPRSTP# = 1
FN9199.2
May 15, 2006
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet ISL6262.PDF ] | |
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