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PDF CY8CLED04D01 Data sheet ( Hoja de datos )
| Número de pieza | CY8CLED04D01 | |
| Descripción | PowerPSoC Intelligent LED Driver | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY8CLED04D01, CY8CLED04D02
CY8CLED04G01, CY8CLED03D01
CY8CLED03D02, CY8CLED03G01
CY8CLED02D01, CY8CLED01D01
PowerPSoC® Intelligent LED Driver
1. Features
■ Integrated Power Peripherals
❐ Four internal 32V low side N-Channel power
FETs
• RDS(ON)– 0.5Ω for 1.0A devices
• Up to 2 MHz configurable switching frequency
❐ Four hysteretic controllers
• Independently programmable upper and
lower thresholds
• Programmable minimum on/off timers
❐ Four low side gate drivers with programmable
drive strength
❐ Four precision high side current sense amplifiers
❐ Three 16-bit LED dimming modulators: PrISM,
DMM, and PWM
❐ Six fast response (100 ns) voltage comparators
❐ Six 8-bit reference DACs
❐ Built-in switching regulator eliminates external
5V supply
❐ Multiple topologies including floating load buck,
floating load buck-boost, and boost
■ M8C CPU Core
❐ Processor speeds up to 24 MHz
■ Advanced Peripherals (PSoC® Blocks)
❐ Capacitive sensing application capability
❐ DMX512 interface
❐ DALI interface
❐ I2C master or slave
❐ Full-duplex UARTs
❐ Multiple SPI masters or slaves
❐ Integrated temperature sensor
❐ Up to 12-bit ADCs
❐ 6 to 12-bit incremental ADCs
❐ Up to 9-bit DACs
❐ Programmable gain amplifiers
❐ Programmable filters and comparators
❐ 8 to 32-bit timers and counters
❐ Complex peripherals by combining blocks
❐ Configurable to all GPIO pins
■ Programmable Pin Configurations
❐ 25 mA sink on all GPIO and function pins
❐ Pull up, pull down, high Z, strong, or open drain
drive modes on all GPIO and function pins
❐ Up to 10 analog inputs on GPIO
❐ Two 30 mA analog outputs on GPIO
❐ Configurable interrupt on all GPIO
■ Flexible On-chip Memory
❐ 16K Flash program storage 50,000 erase and
write cycles
❐ 1K SRAM data storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash updates
❐ Flexible protection modes
❐ EEPROM emulation in Flash
■ Complete Development Tools
❐ Free development software: PSoC Designer
5.0™
❐ Full featured, In-Circuit Emulator and Program-
mer
❐ Full speed emulation
❐ Complex breakpoint structure
❐ 128 kBytes trace memory
■ Visual Embedded Design
❐ LED based express drivers
❐ Binning compensation
❐ Temperature feedback
■ Applications
❐ Stage LED lighting
❐ Architectural LED lighting
❐ General purpose LED lighting
❐ Automotive and emergency vehicle LED lighting
❐ Landscape LED lighting
❐ Display LED lighting
❐ Effects LED lighting
❐ Signage LED lighting
■ Device Options
❐ CY8CLED04D0x
• Four internal FETs with 0.5A and 1.0A options
• Four external gate drivers
❐ CY8CLED04G01
• Four external gate drivers
❐ CY8CLED03D0x
• Three internal FETs with 0.5A and 1.0A
options
• Three external gate drivers
❐ CY8CLED03G01
• Three external gate drivers
❐ CY8CLED02D01
• Two 1.0A internal FETs
• Two external gate drivers
❐ CY8CLED01D01
• One 1.0A internal FET
• One external gate driver
■ 56-pin QFN Package
Figure 1-1. PowerPSoC Architectural Block Diagram
Port 2
Port 1
Port 0
Analog
Drivers
FN0
CSA
CSA
SYSTEM BUS
Analog Mux Bus
Global Digital Interconnect
Global Analog Interconnect
PSoC CORE
SRAM
(1 K bytes)
Supervisory ROM Flash Nonvolatile
( SROM)
Memory(16 K)
Interrupt
Controller
CPU
Core
(M
8C)
Sleep and
Watchdog
24 MHz Internal Main
Oscillator( IMO)
Internal Low Speed
Oscillator( ILO)
Multiple Clock Sources
Clock Signals
System Bus
DIGITAL SYSTEM
Digital PSoC Block Array
DBB 00 DBB 01 DCB 02 DCB 03
DBB 01 DBB 11 DCB 12 DCB13
2 Digital Rows
ANALOG SYSTEM
Analog PSoC
Block Array
CT CT
Analog
Ref
SC SC
SC SC
2Analog Columns
AINX
Vref
Logic Core
PrISM/ DMM /
PWM
Decoder
Analog Block
C1
C2
C3
C4
C5
C6
Comparator
Bank
DAC
DAC
DAC
DAC Bank
PWM Controller
Channels( LV)
DAC
Hysteretic
PWM
Gate
Power
Driver(LV) FETs (HV)
GDRV
DAC
Hysteretic
PWM
GDRV
DAC
Hysteretic
PWM
GDRV
DAC
Hysteretic
PWM
GDRV
Digital
Clocks
MACs
(2)
Decimator
( Type2)
I2C
POR and LVD
System Resets
Internal
Voltage
Reference
IO Analog
Multiplexer
www.DataSheet4U.com
PSoC SYSTEM RESOURCES
SW Regulator
CSA
CSA
POWER PERIPHERALS
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-46319 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 20, 2009
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1 page  
CSP0
CSN0
CSP1
CSN1
CSP2
CSN2
FN0{0,1,2,3}
CY8CLED04D01, CY8CLED04D02
CY8CLED04G01, CY8CLED03D01
CY8CLED03D02, CY8CLED03G01
CY8CLED02D01, CY8CLED01D01
Figure 2-4. CY8CLED03G01 Logic Block Diagram
CSA0
DAC0
DAC1
Hysteretic Mode
Controller 0
External
Gate Drive 0
CSA1
DAC2
DAC3
Hysteretic Mode
Controller 1
External
Gate Drive 1
CSA2
DAC4
DAC5
Hysteretic Mode
Controller 2
External
Gate Drive 2
GD 0
GD 1
GD 2
44
6
Digital Mux
Analog Mux
From Analog Mux
AINX
3 Channel PWM/
PrISM/DMM
Auxiliary
Power
Regulator
SREGHVIN
SREGSW
SREGCSP
SREGCSN
SREGFB
SREGCOMP
Global Digital Interconnect
SRAM
1K
Interrupt
Controller
PSoC CORE
Global Analog Interconnect
SROM
Flash 16K
CPU Core (M8C)
Sleep and
Watchdog
Clock Sources
(Includes IMO and ILO)
DIGITAL SYSTEM
Digital
Block
Array
ANALOG SYSTEM
Analog Ref.
Analog
Block Array
PORT2{2}
PORT1{0,1,4,5,7}
PORT0{3,4,5,7}
www.DataSheet4U.com
Digital
Clocks
2 MACs
Decimator Type
2
I2C
POR and LVD
System Resets
SYSTEM RESOURCES
Internal
Analog
Voltage Ref. Input Muxing
Document Number: 001-46319 Rev. *G
Page 5 of 52
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5 Page 
CY8CLED04D01, CY8CLED04D02
CY8CLED04G01, CY8CLED03D01
CY8CLED03D02, CY8CLED03G01
CY8CLED02D01, CY8CLED01D01
4.11 Function Pins (FN0[0:3])
The function I/O pins are a set of dedicated control pins used to
perform system level functions with the power peripheral blocks
of the PowerPSoC. These pins are dynamically configurable,
enabling them to perform a multitude of input and output
functions. These I/Os have direct access to the input and output
of the voltage comparators, input of the hysteretic controller, and
output of the digital PWM blocks for the device. The function I/O
pins are register mapped. The microcontroller can control and
read the state of these pins and the interrupt function.
Some of the key system benefits of the function I/O are:
■ Enabling higher voltage current-sense amplifier as shown in
Figure 4-5
■ Synchronizing dimming of multiple PowerPSoC controllers as
shown in Figure 4-6
■ Programmable fail-safe monitor and dedicated shutdown of
hysteretic controller as shown in Figure 4-7
Along with the above functionality, these I/Os also provide
interrupt functionality enabling intelligent system responses to
power control lighting system status.
Figure 4-5. External CSA and FET Application
External CSA
HVDD
+
- Rsense
{VLED > 32V
.
.
.
Figure 4-6. PowerPSoC in Master/Slave Configuration
PowerPSoC
(Slave 0)
FN0(x)
DIM Hysteretic
Controller
FN0(0)
PowerPSoC
(Master)
FN0(1)
FN0(2)
FN0(3)
PowerPSoC
(Slave 1)
FN0(x) DIM Hysteretic
Controller
PowerPSoC
(Slave 2)
FN0(x) DIM Hysteretic
Controller
PowerPSoC
(Slave 3)
FN0(x)
DIM Hysteretic
Controller
PowerPSoC
FN0(0)
FN0(1)
FN0(2)
FN0(3)
DAC0
DAC1
DAC6
DAC7
Hysteretic Mode
Controller 0
.
.
.
Hysteretic Mode
Controller 3
External
Gate Drive 0
GD 0
External
Gate Drive 3
GD 3
External FET
Figure 4-7. Event Detection
Event Detect FN0(0) Trip
Hysteretic Mode
Controller 0
..
..
..
External
Gate Drive 0
GD0
Event Detect FN0(3) Trip
Hysteretic Mode
Controller 3
External
Gate Drive 3
GD3
www.DataSheet4U.com
Document Number: 001-46319 Rev. *G
Page 11 of 52
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| PDF Descargar | [ Datasheet CY8CLED04D01.PDF ] | |
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