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PDF JZ4730 Data sheet ( Hoja de datos )
| Número de pieza | JZ4730 | |
| Descripción | 32-Bit Microprocessor | |
| Fabricantes | Ingenic | |
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Jz4730
32 Bits Microprocessor
Data Sheet
Revision: 1.1
Date: Aug. 2006
1 page  
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Overview
1 Overview
Jz4730 is a 32 Bits RISC processor targeting for handheld and general embedded applications.
Incorporate the JzRISC core based on leading micro architecture technology, this processor
provides high integration, high performance and low power consumption solution for embedded
device.
The JzRISC is the advanced and power-efficient 32-bit RISC core with 16K I-Cache and 16K
D-Cache in this processor, operating at speeds up to 400MHz. On-chip modules such as LCD
controller, AC97/I2S controller and camera interface offer designers a rich suite of peripherals for
multimedia application. The memory interface supports a variety of memory types that allow flexible
design requirements, include the glueless connection to NAND Flash for cost sensitive applications.
WLAN, Bluetooth and expansion options are provided through the PCMCIA/CF, USB, and MMC/SD
host controllers. And the other peripherals such as UART, SPI, and Ethernet controller as well as
general-system resources provide enough compute and connectivity capability for many
applications. For the processor block diagram, refer to .
1.1 Block Diagram
3.68MHz
Clock
Divider
Core
PLL
GPIO
PWM
I2C
SPI/SSP/uWire
UART *4
IrDa
Smart Card*2
AC97/I2S
MMC/SD
A
P
B
Clock/Power
Interrupt
OS Timer
Watch Dog
RTC
JzRISC
• 400MHz
• 16K+16K
AHB
External Memory Controller
SRAM
Controller
SDRAM
Controller
NandFlash PCMCIA/CF
Controller Controller
JTAG
Ethernet
MAC
USB 1.1
Host
USB 1.1
Device
LCD
Controller
CCIR656
In/Out
Figure 1-1 Jz4730 Diagram
Jz4730 32 Bits Microprocessor Data Sheet, Revision 1.0
Copyright® 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
3
5 Page 
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2.3 Package
Packaging and Pinout Information
Top View
Side View
Bottom View
Notes:
△1. 5 Dimension is measured at the
maximum solder ball diameter,
parallel to primary datum C
△2. 6 Primary datum C and seating
plane are defined by the spherical
crowns of the solder balls
3. Package outline – 20 x 20 matrix,
17.00mm x 17.00mm x 1.40mm,
0.70mm mold cap, 0.46mm ball,
0.80mm pitch, laminate substrate
Figure 2-1 Jz4730 package
Jz4730 32 Bits Microprocessor Data Sheet, Revision 1.0
Copyright® 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
9
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet JZ4730.PDF ] | |
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