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PDF AD9548 Data sheet ( Hoja de datos )
| Número de pieza | AD9548 | |
| Descripción | Quad/Octal Input Network Clock Generator/Synchronizer | |
| Fabricantes | Analog Devices | |
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Data Sheet
Quad/Octal Input Network Clock
Generator/Synchronizer
AD9548
FEATURES
APPLICATIONS
Supports Stratum 2 stability in holdover mode
Supports reference switchover with phase build-out
Supports hitless reference switchover
Auto/manual holdover and reference switchover
4 pairs of reference input pins with each pair configurable as
a single differential input or as 2 independent single-
ended inputs
Input reference frequencies from 1 Hz to 750 MHz
Reference validation and frequency monitoring (1 ppm)
Programmable input reference switchover priority
30-bit programmable input reference divider
4 pairs of clock output pins with each pair configurable as a
single differential LVDS/LVPECL output or as 2 single-
ended CMOS outputs
Output frequencies up to 450 MHz
30-bit integer and 10-bit fractional programmable feedback
divider
Programmable digital loop filter covering loop bandwidths
from 0.001 Hz to 100 kHz
Optional low noise LC-VCO system clock multiplier
Optional crystal resonator for system clock input
On-chip EEPROM to store multiple power-up profiles
Software controlled power-down
88-lead LFCSP package
Network synchronization
Cleanup of reference clock jitter
GPS 1 pulse per second synchronization
SONET/SDH clocks up to OC-192, including FEC
Stratum 2 holdover, jitter cleanup, and phase transient
control
Stratum 3E and Stratum 3 reference clocks
Wireless base station controllers
Cable infrastructure
Data communications
GENERAL DESCRIPTION
The AD9548 provides synchronization for many systems,
including synchronous optical networks (SONET/SDH). The
AD9548 generates an output clock synchronized to one of up to
four differential or eight single-ended external input references.
The digital PLL allows for reduction of input time jitter or phase
noise associated with the external references. The AD9548
continuously generates a clean (low jitter), valid output clock
even when all references have failed by means of a digitally
controlled loop and holdover circuitry.
The AD9548 operates over an industrial temperature range of
−40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
STABLE
SOURCE
ANALOG
FILTER
CLOCK
MULTIPLIER
REFERENCE INPUTS
AND
MONITOR MUX
AD9548
DIGITAL
PLL
DAC
SYNC
CLOCK DISTRIBUTION
CHANNEL 0
DIVIDER
CHANNEL 1
DIVIDER
CHANNEL 2
DIVIDER
CHANNEL 3
DIVIDER
SERIAL CONTROL INTERFACE
(SPI or I2C)
EEPROM
STATUS AND
CONTROL PINS
Figure 1.
Rev. G
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9548
Data Sheet
SPECIFICATIONS
Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ)
values apply for AVDD3 = DVDD_I/O = 3.3 V; AVDD = DVDD = 1.8 V; TA= 25°C; IDAC = 20 mA (full scale), unless otherwise noted.
SUPPLY VOLTAGE
Table 1.
Parameter
SUPPLY VOLTAGE
DVDD3
DVDD
AVDD3
3.3 V Supply (Typical)
1.8 V Supply (Alternative)
AVDD
Min Typ Max Unit Test Conditions/Comments
3.135 3.30 3.465 V
1.71 1.80 1.89 V
3.135 3.30 3.465 V
3.135 3.30 3.465 V
1.71 1.80 1.89 V
1.71 1.80 1.89 V
Pin 7, Pin 82
Pin 1, Pin 6, Pin 12, Pin 14, Pin 15, Pin 77, Pin 83, Pin 88
Pin 21, Pin 22, Pin 47, Pin 60, Pin 66, Pin 67, Pin 73
Pin 31, Pin 37, Pin 38, Pin 44
Pin 31, Pin 37, Pin 38, Pin 44
Pin 23, Pin 24, Pin 29, Pin 34, Pin 41, Pin 50, Pin 55, Pin 59,
Pin 63, Pin 70, Pin 74
SUPPLY CURRENT
The test conditions for the maximum (max) supply current are the same as the test conditions for the All Blocks Running parameter of Table 3.
The test conditions for the typical (typ) supply current are the same as the test conditions for the Typical Configuration parameter of Table 3.
Table 2.
Parameter
SUPPLY CURRENT
IDVDD3
IDVDD
IAVDD3
IAVDD3
3.3 V Supply (Typical)
1.8 V Supply (Alternative)
IAVDD
Min Typ Max Unit Test Conditions/Comments
1.5 3
mA Pin 7, Pin 82
190 215 mA Pin 1, Pin 6, Pin 12, Pin 14, Pin 15, Pin 77, Pin 83, Pin 88
52 75 mA Pin 21, Pin 22, Pin 47, Pin 60, Pin 66, Pin 67, Pin 73
24 110 mA Pin 31, Pin 37, Pin 38, Pin 44
24 110 mA Pin 31, Pin 37, Pin 38, Pin 44
135 163 mA Pin 23, Pin 24, Pin 29, Pin 34, Pin 41, Pin 50, Pin 55, Pin 59,
Pin 63, Pin 70, Pin 74
POWER DISSIPATION
Table 3.
Parameter
POWER DISSIPATION
Typical Configuration
All Blocks Running
Full Power-Down
Min Typ Max Unit Test Conditions/Comments
800 1100 mW fSYSCLK = 20 MHz1; fS = 1 GHz2; fDDS = 122.88 MHz3; one
LVPECL clock distribution output running at 122.88 MHz
(all others powered down); one input reference running
at 100 MHz (all others powered down)
900 1400 mW fSYSCLK = 20 MHz1; fS = 1 GHz2; fDDS = 399 MHz3; all clock
distribution outputs configured as LVPECL at 399 MHz; all
input references configured as differential at 100 MHz;
fractional-N active (R = 10, S = 39, U = 9, V = 10)
13 mW Conditions = typical configuration; no external pull-up or
pull-down resistors
Rev. G | Page 4 of 111
5 Page 
AD9548
Data Sheet
TIME DURATION OF DIGITAL FUNCTIONS
Table 13.
Parameter
Min
TIME DURATION OF DIGITAL FUNCTIONS
EEPROM-to-Register Download Time
Register-to-EEPROM Upload Time
Minimum Power-Down Exit Time
Maximum Time from Assertion of the RESET
pin to the M0 to M7 Pins Entering High
Impedance State
DIGITAL PLL
Table 14.
Parameter
Min
DIGITAL PLL
Phase-Frequency Detector (PFD)
Input Frequency Range
Loop Bandwidth
1
0.001
Phase Margin
Reference Input (R) Division Factor
Integer Feedback (S) Division Factor
Fractional Feedback Divide Ratio
30
1
8
0
Typ
Typ Max Unit Test Conditions/Comments
25 ms Using default EEPROM storage
sequence (see Register 0x0E10 to
Register 0x0E3F)
200 ms Using default EEPROM storage
sequence (see Register 0x0E10 to
Register 0x0E3F
10.5 μs Dependent on loop-filter bandwidth
45 ns
Max
107
105
89
230
230
0.999
Unit
Hz
Hz
Degrees
Test Conditions/Comments
Maximum fPFD1: fS/1002
Programmable design parameter; maximum
fLOOP = fREF/(20R)3
Programmable design parameter
1, 2, …, 1,073,741,824
8, 9, …, 1,073,741,824
Maximum value: 1022/1023
1 fPFD is the frequency at the input to the phase-frequency detector.
2 fS is the sample rate of the output DAC.
3 fREF is the frequency of the active reference; R is the frequency division factor determined by the R-divider.
DIGITAL PLL LOCK DETECTION
Table 15.
Parameter
PHASE LOCK DETECTOR
Threshold Programming Range
Threshold Resolution
FREQUENCY LOCK DETECTOR
Threshold Programming Range
Threshold Resolution
Min
0.001
0.001
Typ
1
1
Max Unit
65.5 ns
ps
16,700 ns
ps
Test Conditions/Comments
Reference-to-feedback period difference
HOLDOVER SPECIFICATIONS
Table 16.
Parameter
HOLDOVER SPECIFICATIONS
Frequency Accuracy
Min
Typ
<0.01
Max
Unit
ppb
Test Conditions/Comments
Excludes frequency drift of SYSCLK source;
excludes frequency drift of input reference prior
to entering holdover
Rev. G | Page 10 of 111
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9548.PDF ] | |
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