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PDF CY7B9930V Data sheet ( Hoja de datos )
| Número de pieza | CY7B9930V | |
| Descripción | (CY7B9930V / CY7B9940V) High Speed Multifrequency PLL Clock Buffer | |
| Fabricantes | Cypress Semiconductor | |
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RoboClockII™ Junior,
CY7B9930V, CY7B9940V
High Speed Multifrequency
PLL Clock Buffer
Features
■ 12–100 MHz (CY7B9930V), or 24–200 MHz (CY7B9940V)
input/output operation
■ Matched pair output skew < 200 ps
■ Zero input-to-output delay
■ 10 LVTTL 50% duty-cycle outputs capable of driving 50ω
terminated lines
■ Commercial temperature range with eight outputs at 200
MHz
■ Industrial temperature range with eight outputs at 200 MHz
■ 3.3V LVTTL/LV differential (LVPECL), fault-tolerant and hot
insertable reference inputs
■ Multiply ratios of (1–6, 8, 10, 12)
■ Operation up to 12x input frequency
■ Individual output bank disable for aggressive power
management and EMI reduction
■ Output high impedance option for testing purposes
■ Fully integrated PLL with lock indicator
■ Low cycle-to-cycle jitter (<100 ps peak-peak)
■ Single 3.3V ± 10% supply
■ 44-pin TQFP package
Functional Description
The CY7B9930V and CY7B9940V High-Speed Multifrequency
PLL Clock Buffers offer user-selectable control over system
clock functions. This multiple output clock driver provides the
system integrator with functions necessary to optimize the timing
of high performance computer or communication systems.
Ten configurable outputs can each drive terminated transmission
lines with impedances as low as 50Ω while delivering minimal and
specified output skews at LVTTL levels. The outputs are arranged
in three banks. The FB feedback bank consists of two outputs,
which allows divide-by functionality from 1 to 12. Any one of
these ten outputs can be connected to the feedback input as well
as driving other inputs.
Selectable reference input is a fault tolerance feature that allows
smooth change over to secondary clock source, when the
primary clock source is not in operation. The reference inputs are
configurable to accommodate both LVTTL or differential
(LVPECL) inputs. The completely integrated PLL reduces jitter
and simplifies board layout.
Block Diagram
FBKA
REFA+
REFA–
REFB+
REFB–
REFSEL
Phase
Freq.
Detector
Filter
FS 3
Output_Mode 3
Feedback Bank FBDS0 3
FBDS1 3
Divide
Matrix
Bank 2
DIS2
Bank 1
DIS1
VCO
Control Logic
Divide
Generator
LOCK
QFA0
QFA1
2QA0
2QA1
2QB0
2QB1
1QA0
1QA1
1QB0
1QB1
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-07271 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 8, 2007
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RoboClockII™ Junior,
CY7B9930V, CY7B9940V
Absolute Maximum Conditions
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ...........................................−40°C to +125°C
Ambient Temperature with power applied ........−40°C to +125°C
Supply voltage to ground potential ........................−0.5V to +4.6V
DC input voltage ............................................... −0.3V to VCC+0.5V
Output current into outputs (LOW) ...................................40 mA
Static discharge voltage................................................. >2000V
MIL-STD-883, Method 3015)
Latch up current......................................................... >±200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VCC
3.3V ±10%
3.3V ±10%
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Max.
Unit
LVTTL Compatible Output Pins (QFA[0:1], [1:4]Q[A:B][0:1], LOCK)
VOH LVTTL HIGH voltage QFA[0:1], [1:2]Q[A:B][0:1] VCC = Min., IOH = –30 mA
LOCK
IOH = –2 mA, VCC = Min.
VOL
LVTTL LOW voltage QFA[0:1], [1:2]Q[A:B][0:1]
VCC = Min., IOL= 30 mA
LOCK
IOL= 2 mA, VCC = Min.
IOZ High impedance state leakage current
LVTTL Compatible Input Pins (FBKA, REFA±, REFB±, REFSEL, DIS[1:2])
2.4
2.4
–
–
–100
–
–
0.5
0.5
100
V
V
V
V
μA
VIH LVTTL Input HIGH FBKA+, REF[A:B]±
REFSEL, DIS[1:2]
VIL LVTTL Input LOW FBKA+, REF[A:B]±
REFSEL, DIS[1:2]
Min. < VCC < Max.
Min. < VCC < Max.
2.0
2.0
–0.3
–0.3
VCC+0.3
VCC+0.3
0.8
0.8
V
V
V
V
II
LVTTL VIN >VCC
FBKA+, REF[A:B]±
VCC = GND, VIN = 3.63V
–
100 μA
IlH LVTTL Input HIGH FBKA+, REF[A:B]±
Current
REFSEL, DIS[1:2]
VCC = Max., VIN = VCC
VIN = VCC
–
–
500 μA
500 μA
IlL
LVTTL Input LOW FBKA+, REF[A:B]±
VCC = Max., VIN = GND
–500
–
μA
Current
REFSEL, DIS[1:2]
–500
–
μA
3-Level Input Pins (FBDS[0:1], FS, Output_Mode)
VIHH
VIMM
VILL
Three level input HIGH[4]
Three level input MID[4]
Three level input LOW[4]
IIHH Three level input Three level input pins
HIGH current
Min. < VCC < Max.
Min. < VCC < Max.
Min. < VCC < Max.
VIN = VCC
0.87*VCC
0.47*VCC
–
–
0.53*VCC
0.13*VCC
200
V
V
V
μA
IIMM Three level input MID Three level input pins
current
VIN = VCC/2
–50 50
μA
IILL Three level input Three level input pins
LOW current
VIN = GND
–200
–
μA
LVDIFF Input Pins (REF[A:B]±)
VDIFF
Input differential voltage
400 VCC mV
VIHHP
Highest input HIGH voltage
1.0 VCC
V
VILLP
Lowest input LOW voltage
GND VCC – 0.4
V
VCOM
Common mode range (crossing voltage)
0.8 VCC
V
Note
4. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold the
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before
all data sheet limits are achieved.
Document Number: 38-07271 Rev. *C
Page 5 of 11
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RoboClockII™ Junior,
CY7B9930V, CY7B9940V
Document History Page
Document Title: RoboClockII™ Junior, CY7B9930V, CY7B9940V High Speed Multifrequency PLL Clock Buffer
Document Number: 38-07271
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
110536 12/02/01
SZV Change from Spec number: 38-01141
*A
115109 7/03/02
HWT Add 44TQFP package for both CY7B9930/40V – Industrial Operating Range
*B
128463 7/29/03
RGL Added clock input frequency (fin) specifications in the switching characteristics
table.
Added Min. values for the clock output frequency (fout) in the switching charac-
teristics table.
*C 1346903 8/8/07 WWZ/VED/ Update the ordering info to reflect the current status and Pb-free part numbers.
ARI Implemented new template. Updated the package diagram.
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07271 Rev. *C
Revised August 8, 2007
Page 11 of 11
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
trademarks referenced herein are property of the respective corporations.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips.
All products and company names mentioned in this document may be the trademarks of their respective holders.
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