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PDF LMH0307 Data sheet ( Hoja de datos )
| Número de pieza | LMH0307 | |
| Descripción | 3 Gbps HD/SD SDI Dual Cable Driver | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
June 26, 2008
LMH0307
3 Gbps HD/SD SDI Dual Cable Driver with Cable Detect
General Description
The LMH0307 3 Gbps HD/SD SDI Dual Cable Driver with
Cable Detect is designed for use in SMPTE 424M, SMPTE
292M, SMPTE 344M, and SMPTE 259M serial digital video
applications. The LMH0307 implements two complementary
output drivers and drives 75Ω transmission lines (Belden
1694A, Belden 8281, or equivalent) at data rates up to 2.97
Gbps.
The LMH0307 includes intelligent sensing capabilities to im-
prove system diagnostics. The cable detect feature senses
near-end termination to determine if a cable is correctly at-
tached to the output BNC. Input loss of signal (LOS) detects
the presence of a valid signal at the input of the cable driver.
These sensing features may be used to alert the user of a
system fault and activate a deep power save mode, reducing
the cable driver's power consumption to 3 mW. These fea-
tures are accessible via an SMBus interface.
The LMH0307 provides two selectable slew rates for SMPTE
259M and SMPTE 424M / 292M compliance. The output am-
plitude is adjustable ±10% in 5 mV steps via the SMBus.
The LMH0307 is powered from a single 3.3V supply. Power
consumption is typically 230 mW in SD mode and 275 mW in
HD mode. The LMH0307 is available in a 16-pin LLP pack-
age.
The LMH0307 interfaces with National's LMH0356 for addi-
tional system control and power consumption savings (see
Typical Application).
Features
■ SMPTE 424M, SMPTE 292M, SMPTE 344M, and SMPTE
259M compliant
■ Data rates to 2.97 Gbps
■ Cable detect on output
■ Loss of signal detect at input
■ Output driver power down control
■ Typical power consumption: 230 mW in SD mode and 275
mW in HD mode
■ Power save mode typical power consumption: 4 mW
■ Single 3.3V supply operation
■ Differential input
■ Dual complementary 75Ω outputs
■ Selectable slew rate
■ Industrial temperature range: −40°C to +85°C
■ 16–pin LLP package
Applications
■ SMPTE 424M, SMPTE 292M, SMPTE 344M, and SMPTE
259M serial digital interfaces
■ Digital video routers and switches
■ Distribution amplifiers
Typical Application
© 2008 National Semiconductor Corporation 300479
30047903
www.national.com
1 page  
wwPwi.nDatDaSehesect4Uri.cpomtions
Pin Name
1 SDI
2 SDI
3 VEE
4 RREF
5 RSTI
6 ENABLE
7 SDA
8 SCL
9 VCC
10 SD/HD
11 SDO0
12 SDO0
13 FAULT
14 SDO1
15 SDO1
16 RSTO
DAP VEE
Description
Serial data true input.
Serial data complement input.
Negative power supply (ground).
Bias resistor. Connect a 750Ω resistor to VCC.
Reset input.
H = Normal operation.
L = Device reset. The device operates with default register settings. Forcing RSTI low also forces
RSTO low.
Output driver enable (with internal pullup).
H = Normal operation.
L = Output driver powered off.
SMBus bidirectional data pin. When functioning as an output, it is open drain. This pin requires an
external pullup.
SMBus clock input. SCL is input only. This pin requires an external pullup.
Positive power supply (+3.3V).
Output slew rate control.
H = Output rise/fall time complies with SMPTE 259M.
L = Output rise/fall time complies with SMPTE 424M / 292M.
Serial data output 0 complement output.
Serial data output 0 true output.
Fault open drain output flag. Requires external pullup resistor and may be wire ORed with multiple
cable drivers.
H = Normal operation.
L = Loss of signal or termination fault for any output.
Serial data output 1 true output.
Serial data output 1 complement output.
Reset output. RSTO is automatically set to 1 when register 0 is written. It can be reset back to zero
by forcing RSTI to zero to reset the device. Used to daisy chain multiple cable drivers on the same
SMBus.
Connect exposed DAP to negative power supply (ground).
5 www.national.com
5 Page 
Address R/W Name
Bits Field
ww0w5.hDataSRh/eWet4UO.UcoTmPUT0CTRL 7 RSVD
Default Description
0 Reserved as 0. Always write 0 to this bit.
6 FLOSOF
0 Force LOS to always OFF (signal never detected). This forces
the device into either the mute or “add offset” state. The
device will behave as if there is no signal regardless of the
input.
0: LOS operates normally, muting of adding offset as
specified by the MUTE bit.
1: Signal is never detected. Muting or adding offset is always
in place as specified by the MUTE bit.
5 FLOSON
0 Force LOS to always ON (signal always detected). This
prevents the device from muting or adding offset and makes
the LOS have no effect on device operation. (The LOS bit in
register 01h still reflects the state of LOS).
0: LOS operates normally, muting or adding offset as
specified in the MUTE bit.
1: LOS never causes muting or the addition of offset.
4 LOSEN
0 Configures LOS to be combined with the ENABLE
functionality.
0: Only the PD bits and ENABLE pin affect the power down
state of the output drivers.
1: If the ENABLE pin is set to ground, it powers down the
output drivers regardless of the state of LOS or the PD bits.
With the ENABLE pin set to VCC, LOS=0 will power down the
output drivers, and LOS=1 will leave the power down state
dependent on the PD bits.
3 MUTE
0 Selects whether the device will MUTE when loss of signal is
detected or add an offset to prevent self oscillation. When an
input signal is detected (LOS=1), the device will operate
normally.
0: Loss of signal will force a small offset to prevent self
oscillation.
1: Loss of signal will force the channel to MUTE.
2:0 SDTFThresh0
010 Sets the Termination Fault threshold for SDO0, when SD is
set to SD rates (1). Combines with SDTFThresh0LSB in
register 03h (default for combined value is 0100).
06h R/W OUTPUT1
7:5 HDTFThresh1
100 Sets the Termination Fault threshold for SDO1, when SD is
set to HD rates (0). Combines with HDTFThresh1LSB in
register 07h (default for combined value is 1000).
4:0 AMP1
10000 SDO1 output amplitude in roughly 5 mV steps.
07h R/W OUTPUT1CTRL 7 HDTFThresh1LSB 0 Least Significant Bit for HDTFThresh1 detection threshold.
Combines with HDTFThresh1 bits in register 06h.
6 SDTFThresh1LSB 0 Least Significant Bit for SDTFThresh1 detection threshold.
Combines with SDTFThresh1 bits in register 07h.
5:3 RSVD
011 Reserved as 011. Always write 011 to these bits.
2:0 SDTFThresh1
010 Sets the Termination Fault threshold for SDO1, when SD is
set to SD rates (1). Combines with SDTFThresh1LSB in bit 6
(default for combined value is 0100).
11 www.national.com
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| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet LMH0307.PDF ] | |
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