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PDF ADUM4160 Data sheet ( Hoja de datos )
| Número de pieza | ADUM4160 | |
| Descripción | Full/Low Speed 5 kV USB Digital Isolator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Full/Low Speed 5 kV USB Digital Isolator
ADuM4160
FEATURES
USB 2.0 compatible
Low and full speed data rate: 1.5 Mbps and 12 Mbps
Bidirectional communication
4.5 V to 5.5 V VBUS operation
7 mA maximum upstream supply current @ 1.5 Mbps
8 mA maximum upstream supply current @ 12 Mbps
2.3 mA maximum upstream idle current
Upstream short-circuit protection
Class 3A contact ESD performance per ANSI/ESD STM5.1-2007
High temperature operation: 105°C
High common-mode transient immunity: >25 kV/μs
16-lead SOIC wide-body package version
16-lead SOIC wide body enhanced creepage version
RoHS compliant
Safety and regulatory approvals (RI-16 package)
UL recognition: 5000 V rms for 1 minute per
UL 1577
CSA Component Acceptance Notice #5A
IEC 60601-1: 250 V rms (reinforced)
IEC 60950-1: 400 V rms (reinforced)
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 846 V peak
APPLICATIONS
USB peripheral isolation
Isolated USB hub
Medical applications
GENERAL DESCRIPTION
The ADuM41601 is a USB port isolator, based on Analog Devices,
Inc., iCoupler® technology. Combining high speed CMOS and
monolithic air core transformer technology, these isolation
components provide outstanding performance characteristics
and are easily integrated with low and full speed USB-compatible
peripheral devices.
FUNCTIONAL BLOCK DIAGRAM
VBUS1 1
GND1 2
VDD1 3
REG
REG 16 VBUS2
15 GND2
14 VDD2
PDEN 4
SPU 5
13 SPD
12 PIN
UD– 6
UD+ 7
GND1 8
PU LOGIC
PD LOGIC
11 DD–
10 DD+
9 GND2
Figure 1.
Many microcontrollers implement USB so that it presents only
the D+ and D− lines to external pins. This is desirable in many
cases because it minimizes external components and simplifies
the design; however, this presents particular challenges when
isolation is required. USB lines must automatically switch between
actively driving D+/D−, receiving data, and allowing external
resistors to set the idle state of the bus. The ADuM4160 provides
mechanisms for detecting the direction of data flow and control
over the state of the output buffers. Data direction is determined
on a packet-by-packet basis.
The ADuM4160 uses the edge detection based iCoupler tech-
nology in conjunction with internal logic to implement a
transparent, easily configured, upstream facing port isolator.
Isolating an upstream facing port provides several advantages
in simplicity, power management, and robust operation.
The isolator has propagation delay comparable to that of a
standard hub and cable. It operates with the bus voltage on
either side ranging from 4.5 V to 5.5 V, allowing connection
directly to VBUS by internally regulating the voltage to the signaling
level. The ADuM4160 provides isolated control of the pull-up
resistor to allow the peripheral to control connection timing.
The device has a low idle current; so a suspend mode is not
required. A 2.5 kV version, the ADuM3160, is also available.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,329.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009–2012 Analog Devices, Inc. All rights reserved.
1 page  
Data Sheet
ADuM4160
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
4.5 V ≤ VBUS1 ≤ 5.5 V, 4.5 V ≤ VBUS2 ≤ 5.5 V; 3.1 V ≤ VDD1 ≤ 3.6 V, 3.1 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over
the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Each
voltage is relative to its respective ground.
Table 1.
Parameter
Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Total Supply Current1
1.5 Mbps
VDD1 or VBUS1 Supply Current
IDD1 (L)
5 7 mA 750 kHz logic signal rate CL = 450 pF
VDD2 or VBUS2 Supply Current
IDD2 (L)
5 7 mA 750 kHz logic signal rate CL = 450 pF
12 Mbps
VDD1 or VBUS1 Supply Current
IDD1 (F)
6 8 mA 6 MHz logic signal rate CL = 50 pF
VDD2 or VBUS2 Supply Current
IDD2 (F)
6 8 mA 6 MHz logic signal rate CL = 50 pF
Idle Current
VDD1 or VBUS1 Idle Current
IDD1 (I)
1.7 2.3 mA
Input Currents
IDD−, IDD+,
IUD+, IUD−,
ISPD, IPIN,
ISPU, IPDEN
−1
+0.1 +1 μA 0 V ≤ VDD−, VDD+, VUD+, VUD−, VSPD, VPIN,
VSPU, VPDEN ≤ 3.0
Single-Ended Logic High Input Threshold VIH 2.0
V
Single-Ended Logic Low Input Threshold
VIL
0.8 V
Single-Ended Input Hysteresis
VHST 0.4 V
Differential Input Sensitivity
VDI 0.2
V |VXD+ − VXD−|
Logic High Output Voltages
VOH 2.8
3.6 V RL = 15 kΩ, VL = 0 V
Logic Low Output Voltages
VOL 0
0.3 V RL = 1.5 kΩ, VL = 3.6 V
VDD1 and VDD2 Supply Undervoltage Lockout
VUVLO
2.4
3.1 V
VBUS1 Supply Undervoltage Lockout
VUVLOB1
3.5
4.35 V
VBUS2 Supply Undervoltage Lockout
VUVLOB2
3.5
4.4 V
Transceiver Capacitance
CIN 10 pF UD+, UD−, DD+, DD− to ground
Capacitance Matching
10 %
Full Speed Driver Impedance
ZOUTH
4
20 Ω
Impedance Matching
10 %
SWITCHING SPECIFICATIONS, I/O PINS LOW SPEED
Low Speed Data Rate
Propagation Delay2
tPHLL, tPLHL
1.5 Mbps CL = 50 pF
325 ns CL = 50 pF, SPD = SPU = low,
VDD1, VDD2 = 3.3 V
Side 1 Output Rise/Fall Time (10% to 90%) Low
Speed
tRL/tFL
75
300 ns CL = 450 pF, SPD = SPU = low,
VDD1, VDD2 = 3.3 V
Low Speed Differential Jitter, Next Transition
|tLJN|
45 ns CL = 50 pF
Low Speed Differential Jitter, Paired Transition |tLJP|
15 ns CL = 50 pF
SWITCHING SPECIFICATIONS, I/O PINS FULL SPEED
Full Speed Data Rate
Propagation Delay2
12 Mbps CL = 50 pF
tPHLF, tPLHF 20 60 70 ns CL = 50 pF, SPD = SPU = high,
VDD1, VDD2 = 3.3 V
Output Rise/Fall Time (10% to 90%) Full Speed tRF/tFF
4
20 ns CL = 50 pF, SPD = SPU = high,
VDD1, VDD2 = 3.3 V
Full Speed Differential Jitter, Next Transition
|tFJN|
3 ns CL = 50 pF
Full Speed Differential Jitter, Paired Transition
|tFJP|
1 ns CL = 50 pF
Rev. D | Page 3 of 16
5 Page 
Data Sheet
ADuM4160
Table 10. Truth Table, Control Signals, and Power (Positive Logic)1
VSPU
VBUS1, VDD1
Input State
VUD+,
VUD−
State
VSPD
VBUS2, VDD2
Input State
VDD+,
VDD−
State
VPIN
Input
H
Powered Active H
Powered
Active H
L
Powered Active L
Powered
Active H
L
Powered Active H
Powered
Active H
H Powered Active L
Powered
Active H
X Powered Z
X
Powered
Z
L
X Unpowered X
X
Powered
Z
X
X Powered Z
X Unpowered X
X
Notes
Input and output logic set for full speed logic convention
and timing.
Input and output logic set for low speed logic convention
and timing.
Not allowed: VSPU and VSPD must be set to the same value.
USB host detects communications error.
Not allowed: VSPU and VSPD must be set to the same value.
USB host detects communications error.
Upstream Side 1 presents a disconnected state to the USB
cable.
When power is not present on VDD1, the downstream data
output drivers revert to high-Z within 32 bit times. The
downstream side initializes in high-Z state.
When power is not present on VDD2, the upstream side
disconnects the pull-up and disables the upstream drivers
within 32 bit times.
1 H represents logic high input or output, L represents logic low input or output, X represents the don’t care logic input or output, and Z represents the high impedance
output state.
Rev. D | Page 9 of 16
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ADUM4160.PDF ] | |
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