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PDF APL0760 Data sheet ( Hoja de datos )

Número de pieza APL0760
Descripción PLL Module
Fabricantes Advanced Semiconductor Business 
Logotipo Advanced Semiconductor Business Logotipo



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No Preview Available ! APL0760 Hoja de datos, Descripción, Manual

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Features
· +5 dBm Output Level at 760 MHz
· Channel Step Size : 20 kHz
· 2nd Harmonic : < -25 dBc
· Spurious Level : < -70 dBc
· Lock Time : < 10 ms
· 18 mA Current Consumption
Description
The plerowTM PLL synthesizer module was
designed for use in wireless and wireline
systems in a wide range of frequency from
50 MHz to 6 GHz. ASB’s PLL provides
exceptionally low spurious and phase noise
performance with fast locking time and low
current consumption. All products are
available in a surface-mount type package.
Specifications
Parameter
Unit Min.
Typical
Max.
Frequency Range
MHz
760
Output Power
dBm
4
5
6
Supply Voltage
V 4.7 5.0 5.3
Current Consumption
mA
18 30
Channel Step Size
kHz
20
2nd Harmonics
dBc
-35 -25
Spurious Level
dBc
-78 -70
Lock Time
ms
3 10
Reference Frequency
MHz
10
Reference Input Level
dBm
-5
0
5
Phase Noise (C / N)
@ 10 kHz
dBc/Hz
-111
-108
-105
@ 100 kHz
Output Impedance
Operating Temp. Range
Package Type & Size
dBc/Hz
°C
mm
-124
-121
-118
50
-40 25
85
SMT, 19.0W×19.0L×5.8H
1) Measurement conditions are as follows: T = 25°C, VCC = 5 V, Freq. = 760 MHz, 50 ohm system.
Plerow APL0760
PLL Module
More Information
Website: www.asb.co.kr
Tel: (82) 42-528-7220
Fax: (82) 42-528-7222
ASB, Inc., 4th Fl. Venture Town
Bldg, KT HRDC, 367-17
Goijeong-Dong, Seo-Gu,
Daejeon, 302-716, Korea
Outline Drawing
Top View
A
C
B
Side View
Bottom View
I
HG
D
E
F
Pin Configuration
1 CLOCK
2 DATA
3 ENABLE
4 OSC IN
9 VCC (VCO)
13 RF OUT
15 VCP (PLL)
16 LOCK DETECT
Others
Ground
Dimension (mm)
A 19.0
B 19.0
C 5.8
D 1.5
E 0.5
F 1.75
G 1.35
H 15.0
I 0.9
Tolerance: ± 0.2
1/1
www.asb.co.kr
March 2004

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