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PDF ADN4600 Data sheet ( Hoja de datos )
| Número de pieza | ADN4600 | |
| Descripción | Asynchronous Crosspoint Switch | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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4.25 Gbps, 8 × 8,
Asynchronous Crosspoint Switch
ADN4600
FEATURES
Full 8 × 8 crossbar connectivity
Fully buffered signal path supports multicast and broadcast
operation
Optimized for dc to 4.25 Gbps data
Programmable receive equalization
Compensates for up to 30 in. of FR4 @ 4.25 Gbps
Programmable transmit pre-emphasis/de-emphasis
Compensates for up to 30 in. of FR4 @ 4.25 Gbps
Flexible 1.8 V to 3.3 V core supply
Per lane positive/negative (P/N) pair inversion for routing ease
Low power: 125 mW/channel at 4.25 Gbps
DC- or ac-coupled differential CML inputs
Programmable CML output levels
50 Ω on-chip termination
−40°C to +85°C temperature range operation
Supports 8b10b, scrambled or uncoded nonreturn-to-zero
(NRZ) data
I2C control interface
Package: 64-lead LFCSP
APPLICATIONS
1×, 2×, 4× FibreChannel
XAUI
Gigabit Ethernet over backplane
10GBase-CX4
InfiniBand®
50 Ω cables
GENERAL DESCRIPTION
The ADN4600 is an asynchronous, nonblocking crosspoint
switch with eight differential PECL-/CML-compatible inputs
with programmable equalization and eight differential CML
outputs with programmable output levels and pre-emphasis or
de-emphasis. The operation of this device is optimized for NRZ
data at rates up to 4.25 Gbps.
The receive inputs provide programmable equalization with
nine settings to compensate for up to 30 in. of FR4 and
programmable pre-emphasis with seven settings to compensate
for up to 30 in. of FR4 at 4.25 Gbps.
IP[7:0]
IN[7:0]
FUNCTIONAL BLOCK DIAGRAM
RECEIVE
EQUALIZATION
CROSSPOINT
ARRAY
ADN4600
TRANSMIT
PRE-EMPHASIS
EQ PE
OP[7:0]
ON[7:0]
ADDR[1:0]
SCL
SDA
RESETB
CONTROL LOGIC
Figure 1.
The ADN4600 nonblocking switch core implements an 8 × 8
crossbar and supports independent channel switching through the
I2C control interface. Every channel implements an asynchronous
path supporting NRZ data rates from dc to 4.25 Gbps. Each
channel is fully independent of other channels. The ADN4600
has low latency and very low channel-to-channel skew.
The main application for the ADN4600 is to support switching
on the backplane, line card, or cable interface sides of serial links.
The ADN4600 is packaged in a 9 mm × 9 mm, 64-lead LFCSP
package and operates from −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
1 page  
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TIMING SPECIFICATIONS
Table 2. I2C Timing Parameters
Parameter
Min
Max
fSCL 0 400
tHD;STA
0.6 N/A
tSU;STA
0.6 N/A
tLOW 1.3 N/A
tHIGH 0.6 N/A
tHD;DAT
0 N/A
tSU;DAT
10 N/A
tr 1 300
tf 1 300
tSU;STO
0.6 N/A
tBUF 1 N/A
CIO 5 7
Unit Description
kHz SCL clock frequency
μs Hold time for a start condition
μs Setup time for a repeated start condition
μs Low period of the SCL clock
μs High period of the SCL clock
μs Data hold time
ns Data setup time
ns Rise time for both SDA and SCL
ns Fall time for both SDA and SCL
μs Setup time for a stop condition
ns Bus-free time between a stop and a start condition
Pf Capacitance for each I/O pin
ADN4600
I2C Timing Specifications
SDA
tf
SCL
S
tLOW
tSU:DAT
tf
tHD:STA
tHD:DAT
tf tHD:STA
tHIGH
tSU:STA
Sr
Figure 2. I2C Timing Diagram
tf tBUF
tSU:STO
P
S
Rev. 0 | Page 5 of 5
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ADN4600
Test conditions: VCC = 1.8 V, VEE = 0 V, VTTI = VTTO = VCC, RL = 50 Ω, differential output swing = 800 mV p-p differential, TA = 25°C,
unless otherwise noted.
80 100
70
80
60
50 60
40
30 40 VCC = 3.3V
20 VCC = 1.8V
20
10
0
0 20 40
DATA RATE (Hz)
Figure 19. Deterministic Jitter vs. Data Rate
60
0
1.0 1.5 2.0 2.5 3.0 3.5 4.0
INPUT COMMON MODE (V)
Figure 22. Deterministic Jitter vs. Input Common Mode
100
90
80
70
60
50
40
30
20
10
0
0
0.5 1.0 1.5 2.0
DIFFERENTIAL INPUT SWING (V)
Figure 20. Deterministic Jitter vs. Input Swing
2.5
100
80
60
40
20
0
1.0 1.5 2.0 2.5 3.0 3.5
VCC (V)
Figure 23. Deterministic Jitter vs. Supply Voltage
4.0
100
80
60
40
20
0
–60 –40 –20
0
20 40 60
TEMPERATURE (°C)
80
Figure 21. Deterministic Jitter vs. Temperature
100
100
80
60
VCC = 1.8V
40
VCC = 3.3V
20
0
1.0 1.5 2.0 2.5 3.0 3.5 4.0
VTTO (V)
Figure 24. Deterministic Jitter vs. Output Termination Voltage
Rev. 0 | Page 11 of 11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet ADN4600.PDF ] | |
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