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PDF MB90488B Data sheet ( Hoja de datos )
| Número de pieza | MB90488B | |
| Descripción | (MB90480B / MB90485B) 16-bit Microcontroller | |
| Fabricantes | Fujitsu Media Devices | |
| Logotipo |  |
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FUJITSU MICROELECTRONICS
DATA SHEET
DS07-13722-9Ea
16-bit Microcontroller
CMOSwww.datasheet4u.com
F2MC-16LX MB90480B/485B Series
MB90F481B/F482B/487B/488B/483C
MB90F488B/F489B/V480B/V485B
■ DESCRIPTION
The MB90480B/485B series is a 16-bit general-purpose FUJITSU MICROELECTRONICS microcontroller de-
signed for process control in consumer devices and other applications requiring high-speed real-time processing.
The F2MC-16LX CPU core instruction set retains the AT architecture of the F2MC*1 family, with additional instruc-
tions for high-level languages, expanded addressing mode, enhanced multiply-drive instructions, and complete
bit processing. In addition, a 32-bit accumulator is provided to enable long-word processing.
The MB90480B/485B series features embedded peripheral resources including 8/16-bit PPG, expanded I/O serial
interface, UART, 10-bit A/D converter, 16-bit I/O timer, 8/16-bit up/down-counter, PWC timer, I2C*2 interface, DTP/
external interrupt, chip select, and 16-bit reload timer.
*1 : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
*2 : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these com-
ponents in an I2C system provided that the system conforms to the I2C standard a Specification as defined by
Philips.
■ FEATURES
• Clock
Minimum instruction execution time: 40.0 ns/6.25 MHz base frequency multiplied × 4 (25 MHz internal operating
frequency/3.3 V ± 0.3 V)
62.5 ns/4 MHz base frequency multiplied × 4 (16 MHz internal operating
frequency/3.0 V ± 0.3 V) PLL clock multiplier
• Maximum memory space: 16 Mbytes
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://edevice.fujitsu.com/micom/en-support/
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2002-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2007.11
1 page  
MB90480B/485B Series
(Continued)
Item
Part number MB90487B MB90488B MB90F488B MB90V485B MB90F489B MB90483C
www.dataWshaetecth4du.ocogmtimer
Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(minimum value, at 4 MHz base oscillator)
Low-power
consumption (standby)
modes
Stop mode, sleep mode, CPU intermittent operation mode, watch timer mode, timebase
timer mode
Process
CMOS
Type
3 V/5 V
power
supply*1
3 V/5 V
power
supply*1
3 V/5 V power
supply*1
Included
security
function
3 V/5 V
power
supply*1
3 V/5 V power
supply*1
Included
security
function
3 V/5 V
power
supply*1
Emulator power
supply*3
⎯⎯
⎯ Included ⎯
⎯
*1 : 3 V/5 V I/F pin : All pins should be for 3 V power supply without P20 to P27, P30 to P37, P40 to P47, and
P70 to P77.
*2 : P76/P77 pins are N-ch open drain pins (without P-ch) at built-in I2C. However, MB90V485B uses the N-ch open
drain pin (with P-ch) .
*3 : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used.
Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply
Switching) about details.
Notes : • As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/μPG/I2C
become CMOS input.
• Ensure that you must write to Flash at VCC = 3.13 V to 3.60 V (3.3 V + 10%, − 5%) .
5
5 Page 
MB90480B/485B Series
Pin No.
QFP*1 LQFP*2
www.datasheet4u.com
Pin name
P54
74 72
HRQ
I/O
circuit
type*3
Function
D
(CMOS)
This is a general purpose I/O port. In external bus mode, when the
HDE bit in the EPCR register is set to “1”, this pin functions as the
HRQ pin.
In external bus mode, this pin functions as the hold request input
(HRQ) pin. When the HDE bit in the EPCR register is set to “0”, this
pin functions as a general purpose I/O port.
75 73
P55
HAK
D
(CMOS)
This is a general purpose I/O port. In external bus mode, when the
HDE bit in the EPCR register is set to “1”, this pin functions as the
HAK pin.
In external bus mode, this pin functions as the hold acknowledge
output (HAK) pin. When the HDE bit in the EPCR register is set to
“0”, this pin functions as a general purpose I/O port.
76 74
P56
RDY
D
(CMOS)
This is a general purpose I/O port. In external bus mode, when the
RYE bit in the EPCR register is set to “1”, this pin functions as the
RDY pin.
In external bus mode, this pin functions as the external ready (RDY)
input pin. When the RYE bit in the EPCR register is set to “0”, this
pin functions as a general purpose I/O port.
78 76
This is a general purpose I/O port. In external bus mode, when the
P57 CKE bit in the EPCR register is set to “1”, this pin functions as the
D CLK pin.
(CMOS) In external bus mode, this pin functions as the machine cycle clock
CLK
(CLK) output pin. When the CKE bit in the EPCR register is set to
“0”, this pin functions as a general purpose I/O port.
P60 to P63
38 to 41 36 to 39
AN0 to AN3
H These are general purpose I/O ports.
(CMOS) These are the analog input pins for A/D converter.
P64 to P67
43 to 46 41 to 44
AN4 to AN7
H These are general purpose I/O ports.
(CMOS) These are the analog input pins for A/D converter.
27 25
P70
SIN0
G This is a general purpose I/O port.
(CMOS/H) This is the UART serial data input pin.
28 26
P71
SOT0
F This is a general purpose I/O port.
(CMOS) This is the UART serial data output pin.
29
27
P72
SCK0
G This is a general purpose I/O port.
(CMOS/H) This is the UART serial communication clock I/O pin.
30 28
P73
TIN0
G This is a general purpose I/O port.
(CMOS/H) This is the 16-bit reload timer event input pin.
31 29
P74
TOT0
F This is a general purpose I/O port.
(CMOS) This is the 16-bit reload timer output pin.
(Continued)
11
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