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PDF ARINC429 Data sheet ( Hoja de datos )
| Número de pieza | ARINC429 | |
| Descripción | Bus Interface | |
| Fabricantes | Actel | |
| Logotipo |  |
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ARINC 429 Bus Interface
wwwP.dartaoshdeeut4uc.ctomSummary
Intended Use
• ARINC 429 Transmitter (Tx)
• ARINC 429 Receiver (Rx)
Key Features
• Supports ARINC Specification 429-16
• Configurable up to 16 Rx and 16 Tx Channels
• Programmable FIFO Depth
– Up to 512 Words
• Programmable Interrupt Generation
– Rx and Tx Channels independently
– Up to 64 Words
• Configurable Label Memory Size
– Rx and Tx Channels independently
– Up to 256 Words
• Internal, Wrap-Around Testing
• Software Compatible with Legacy Devices
• Selectable Clock Speed
– 1, 10, 16, or 20 MHz
• Selectable Data Rate on Each Channel
– 12.5 100 kbps
– Optional 50 kbps
• CPU Interface
– Provides Direct CPU Access to Memory
– Simple Interface to Core8051
• Memory
– EDAC Support with RTAX-S Family
• ARINC 429 Bus Interface
– Supports Standard Line Drivers and Receivers
• Available as Integrated Tx and Rx
Supported Families
• Fusion
• ProASIC®3/E
• ProASICPLUS®
• Axcelerator®
• RTAX-S
Core Deliverables
• Evaluation Version
– Compiled RTL Simulation Model, Compliant
with the Actel Libero® Integrated Design
Environment (IDE)
• Netlist Version
– Structural VHDL and Verilog Netlists
• RTL version
– VHDL or Verilog Core Source Code
– Synthesis Scripts
• Verification Testbench – Verilog
• User Testbenches
– Libero IDE Compatible
– VHDL and Verilog
Development System
• Complete ARINC 429 Rx/Tx
• Implementation
– Implemented in an APA600 Device
– Controlled Via an External Terminal Using
Core8051 and RS232 Links
• Includes Line Driver and Receiver Components
Synthesis and Simulation Support
• Directly Supported within the Actel Libero IDE
• Synthesis:
– Synplicity®
– ExemplarTM
– Synopsys®
• Simulation
– Vital-Compliant VHDL Simulators
– OVI-Compliant Verilog Simulators
Verification and Compliance
• Actel-Developed Simulation Testbench
• Core Implemented on the ARINC
Development System
429
September 2006
© 2006 Actel Corporation
v5.0
1
1 page  
ARINC 429 Bus Interface
where NRx is the number of receive channels, NTx is the number of transmit channels, INT is the function to round up
to the next integer, and X and Y are defined in Table 6.
Each Channel Configured Differently
Use EQ 2 to calculate the number of memory blocks required if each channel is configured differently.
www.datasheet4u.com
NTx – 1
NRx – 1
Number of memory blocks = ∑ INT(FIFO_DEPTH[I]/Y + ∑ (INT(LABEL_SIZE[I]/X) + INT(FIFO_DEPTH[I]/Y)),
I=0
I=0
EQ 2
where NRx is the number of receive channels, NTx is the number of transmit channels, INT is the function to round up
to the next integer, and X and Y are defined in Table 6.
Table 6 • Memory Parameters
Device Family
XY
Fusion
512 128
ProASIC3/E
ProASICPLUS
512 128
256 64
Axcelerator/RTAX-S
512 128
Examples for the ProASIC3/E Device Family
If the design has 2 receivers, 1 transmitter, 64 labels for each receiver, 32-words-deep FIFO for each receiver and
transmitter, then
the number of memory blocks = 2 * (INT (64/512) + INT (32/128)) + 1 * INT (32/128) = 2 * (1 + 1) + 1 * (1) = 5.
If the design has 2 receivers, 1 transmitter, 32 labels for receiver # 1, 64 labels for receiver # 2, 32 words-deep FIFO for
receiver # 1, 64-words-deep FIFO for receiver # 2, and 64-words-deep FIFO for transmitter, then
the number of memory blocks = INT (64/128) + (INT (32/512) + INT (32/128)) + (INT (64/512) + INT (64/128))
= 1 + (1 + 1) + (1 + 1) = 5.
Core429 Overview
Core429 provides a complete and flexible interface to a
microprocessor and an ARINC 429 data bus. Connection
to an ARINC 429 data bus requires additional line drivers
and line receivers.
Core429 interfaces to a processor through the internal
memory of the receiver. Core429 can be easily interfaced
to an 8-, 16- or 32-bit data bus. Look-up tables loaded
into memory enable the Core429 receive circuitry to
filter and sort incoming data by label and destination
bits. Core429 supports multiple (configurable) ARINC 429
receiver channels, and each receives data independently.
The receiver data rates (high or low speed) can be
programmed independently. Core429 can decode and
sort data based on the ARINC 429 Label and SDI bits and
stores it in FIFO. Each receiver uses programmable FIFO
to buffer received data. Core429 supports multiple
(configurable) ARINC 429 transmit channels and each
channel can transmit data independently.
Default Mode
This is the recommended mode and allows the user to
configure the core with user-defined transmit and
receive channels.
Functional Description
The core has three main blocks: Transmit, Receive, and
CPU interface. The core can be configured to provide up
to 16 transmit and receive channels.
v5.0
5
5 Page 
ARINC 429 Bus Interface
The address bit 4 is used to determine Rx/Tx as follows:
0 – Rx
1 – Tx
The address bits 5, 6, 7, and 8 are used for decoding the
16 channels as follows:
www.data0s0h0e0et–4uC.choamnnel0
0001 – Channel1
..
..
1110 – Channel14
1111 – Channel15
Table 12 shows the CPU address bit information.
Table 12 • CPU Address Bit Positions
Channel Number
Tx/Rx
Register Index
Byte Index
876543210
MSB 9-Bit CPU Address
LSB
Register Definitions
Rx Registers
Following is the detailed definition of cpu_add [3:2]
decoding and the explanation of Data Register, Control
Register, Status Register, and Label Memory Register
(Table 13 through Table 16 on page 12).
Address Map
00 – Data Register
01 – Control Register
10 – Status Register
11 – Label Memory
Table 13 • Rx Data Register
Bit
Function
Reset State
Type
31:0 Data
0R
Description
Read Data
Table 14 •
Bit
0
1
2
3
4
Rx Control Register
Function
Data rate
Label recognition
Enable 32nd bit as parity
Parity
Decoder
Reset State
0
0
0
0
0
5
Match header bit 9
0
6
Match header bit 10
0
7
Reload label memory
0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Data rate: 0 = 100Kb/s; 1 = 12.5 or 50 Kbps
Label compare: 0 = disable; 1 = enable
0 = 32nd bit is data; 1 = 32nd bit is parity
Parity: 0 = odd; 1 = even
0: SDI bit comparison disabled;
1: SDI bit comparison enabled; ARINC bits 9 and 10 must
match bits 5 and 6 respectively.
If bit 4 is set then this bit should match the ARINC header
bit 9 (SDI bit).
If bit 4 is set then this bit should match the ARINC header
bit 10 (SDI bit).
When bit 7 is set to '1', label memory address pointers are
initialized to '000'. Set this bit to change the contents of
the label memory.
Table 15 •
Bit
0
1
2
Rx Status Register
Function
FIFO empty
FIFO half full or
programmed level
FIFO full
Reset State
0
0
0
Type
R
R
R
Description
0 = not empty; 1 = empty
0 = Less than programmed level; 1 = FIFO is filled at least up
to programmed level
0 = not full; 1 = full
v5.0
11
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| PDF Descargar | [ Datasheet ARINC429.PDF ] | |
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