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PDF DS92UT16TUF Data sheet ( Hoja de datos )
| Número de pieza | DS92UT16TUF | |
| Descripción | UTOPIA-LVDS Bridge | |
| Fabricantes | National Semiconductor | |
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February 2004
DS92UT16TUF
UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data
Transferswww.datasheet4u.com
1.0 General Description
The DS92UT16 is a flexible UTOPIA to LVDS Bridge device.
The LVDS Bridge transparently transports the UTOPIA bus
over a high speed LVDS serial link. The device includes
many reliability features such as an optional 1:1 protection
and built in bit error rate checking.
The parallel interface is user programmable for maximum
flexibility. The user can choose between UTOPIA Level Level
2 ATM layer (master) of PHY layer (slave). The UTOPIA-
LVDS Bridge supports a special MPHY (multi-PHY layer)
operation mode. The MPHY operation supports up to 248
standard UTOPIA Level 2 PHY ports without adding external
circuitry.
The serial interface uses LVDS Serializer and Deserializer
technology. The 16:1 bit serialization allows conveying the
full-duplex parallel bus over two differential transmission
pairs. This enables low cost backplanes and cables. Cable
transmission length can be as long 16 meters.
The serial link carries Flow control information (back pres-
sure) in both directions. The Bridge device applies back
pressure on a per queue basis over the 31 internal FIFO
queues. In addition, the serial link includes an OAM (Opera-
tions and Maintenance) channel that does not detract from
link performance.
There are many applications where the UTOPIA-LVDS
Bridge simplifies designs. Box-to-box connections can use
DS29UT16 devices across cables. Access multiplexor appli-
cations can use the devices across a PCB backplane for
point-to-point and lightly loaded multidrop configurations.
2.0 Features
n 832 Mbps LVDS 16-bit serializer and deserializer
interface
— Suitable for cable, printed circuit board, and
backplane transmission paths
— 10m cable at max LVDS data rate and greater than
16m at min LVDS data rate
— Embedded clock with random data lock capability for
clock recovery
— PRBS (x31 + x28 + 1) based LVDS link BER test
facility
— Two independent LVDS receiver serial ports for
optional 1:1 protection
— Main and redundant LVDS transmit ports
— Loop timing capability enables LVDS recovered clock
to internally drive LVDS transmit clock
— Internal buffers allow maximum LVDS serial bit rate
independent of UTOPIA clock rate
n Programmable UTOPIA interface
— UTOPIA Level 2 up to 52 MHz
— ATM layer or PHY layer interface
— ATM layer interface can support up to 248 standard
Level 2 PHY ports with no additional external
circuitry. Configured as 31 MPHY’s, each with up to 8
sub-ports
— Supports extended cell size up to 64 bytes
— Supports 16- or 8-bit data buses with parity
n Embedded bidirectional, non-blocking flow control over
serial link for per MPHY back pressure
n No external memories required
n Embedded OAM channel over serial link
— Remote Alarm/Status Indications
— Link Trace Label
— Embedded Control Channel with flow control for
software communication
— BIP16 based error performance monitoring
— In protected systems, the standby link OAM channel
is available for embedded communications and
performance/alarm monitoring
n Multiple loop-back options
n Standard microprocessor interface (Intel and Motorola
compatible)
n IEEE 1149.1 JTAG port
n Temperature range: −40˚C to +85˚C
n CMOS technology for low power
n LVDS transceiver section uses 3.3V power supply.
Digital UTOPIA section uses 2.5V power supply. All I/O
are 3.3V tolerant.
n 196 LBGA package, 15x15x1.37 mm, 1.0 mm ball pitch
3.0 Ordering Information
Order Number
DS92UT16TUF
Package Information
196 LBGA package, 15x15x1.37 mm, 1.0 mm ball pitch
Package Number
NUJB0196
© 2004 National Semiconductor Corporation DS200316
www.national.com
1 page  
6.0 Functional Description (Continued)
www.datasheet4u.com
FIGURE 4. Detailed Connection of One Sub-Port for Extended UTOPIA Level 2
20031627
For the purposes of queueing, the 248 PHY ports are con-
figured as sub-ports of the standard 31 ports so each port/
queue has 8 sub-ports as discussed in Section 6.2.2 Up-
Bridge Multi-Port Traffic Buffer. Each MPHY address
corresponds to a port.
The 5 bit MPHY can address up to 31 PHY ports. At least 3
additional bits are required to give the total of 8 bits neces-
sary for addressing 248 PHY ports. These additional ad-
dress bits can be provided by the user in any of the User
Prepend, Cell Header or UDF1/2 bytes of the cell as shown
in Figure 6. The DS92UT16 is configured to extract/insert the
extra address bits from/to any of these bytes.
PHY polling may be carried out as follows:
• Standard UTOPIA Level 2 with 1 CLAV signal.
— One CLAV polling 31 PHY ports.
• DS92UT16 Extended UTOPIA Level 2 with up to 8 CLAV
signals.
— Each CLAV can poll 31 PHY ports giving a total of 248
PHY ports.
Multiple UTOPIA-LVDS bridge devices can be used in par-
allel to share up to 31 PHY ports among PHYs that are on
separate line cards Figure 5. Each of these ports may have
up to 8 sub-ports. There are constraints on the number of
port addresses used per bridge in such a configuration. See
Section 9.2 MULTIPLE BRIDGE MTB CONFIGURATION
5 www.national.com
5 Page 
6.0 Functional Description (Continued)
tial outputs with independent TRI-STATE® controls for each.
The same data is transmitted over both pairs of transmit
pins. The two serial receive interfaces are completely sepa-
rate and independent and are denoted Port A and Port B.
Only one receive port is selected for traffic at any one
time. This is designated the Active Port. The Standby receive
port may be powered down. Alternatively, the Standby re-
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mance monitoring. This allows the condition of the Standby
link to be determined. The LOCK status of both Active and
Standby ports is monitored automatically.
The transmitted data stream contains embedded clock infor-
mation. The receiver’s clock recovery circuit locks onto the
embedded clock in either a random data pattern, or by
instructing the transmitter to send SYNCH patterns. The
DS92LV16 can send SYNCH patterns on power-up or when
synchronization is lost. The latter option requires a feedback
loop in either hardware or software between the transmitter
and the receiver, but has the benefit of a faster lock time. The
LOCK status of both receive ports is reflected on external
pins and alarm/status bits that are readable via the micro-
processor port. The LOCK status, along with the currently
active port, is transmitted to the far-end receiver via the
Remote Alarm and Signalling byte of the OAM channel as
described in Section 6.3.7.1 Remote Alarm and Signaling
Byte. The recovered clocks of both receive ports are avail-
able on external pins.
A Loop Timing option is available whereby the LVDS transmit
clock can be sourced directly from the recovered clock of the
active receiver, rather than from the external transmit clock
input pin.
The transmit port and two receive ports may be indepen-
dently powered down via microprocessor control. Similarly,
the device may be forced to send SYNCH patterns on the
transmit port via microprocessor control.
To assist in designer testing and system commissioning of
the LVDS interface, the DS92UT16 has a built in BER test
facility. The device may be configured to send a PRBS
pattern in place of ATM cells. At the receiver, the device locks
onto this PRBS pattern and provides an error metric.
6.5 CPU INTERFACE
The DS92UT16 contains a flexible microprocessor port ca-
pable of interfacing to any common system processor. Via
this port, the system software can customize the behavior of
the device from the various options provided, monitor the
system performance, and activate diagnostic facilities such
as loop-backs and LVDS BER testing.
In addition to an 8-bit address and 8-bit data bus plus the
associated bus protocol control signals, the port includes an
open-drain interrupt signal. The device may assert this signal
on the detection of various alarms within the device, such as
excessive HEC errors, ECC buffer full/empty, loss of lock
etc. Any of the potential internal sources of this interrupt may
be inhibited individually via an interrupt mask.
A software lock mechanism is implemented to prevent spu-
rious modification of some of the DS92UT16 software acces-
sible registers. A predefined UNLOCK write sequence is
necessary to allow unrestricted software write access to the
DS92UT16. A corresponding LOCK write sequence will pre-
vent any software write access to the these registers. Read
access is unrestricted except as noted in the next paragraph.
See Table 9 for the LOCK and UNLOCK sequences. Only
device configuration registers such as PDU cell length, UTO-
PIA interface mode, etc. are protected in this way. All other
registers associated with the ECC, performance monitoring
and interrupts are always write accessible by the software
except as noted in next paragraph. See Section 18.1 SOFT-
WARE LOCK — 0x00 to 0x01 SLK0 to SLK1.
TABLE 9. Software Lock Sequences
Meaning
Unlock Sequence
LOCK Sequence
Sequence
1st write
2nd write
1st write
2nd write
Address
0x00
0x01
0x00
0x01
Data
0x00
0xFF
0xDE
0xAD
Powering down a Receive Port inhibits access to the asso-
ciated registers. This feature saves power when a Receive
Port is not in use. It allows re-reading the last value read
from a register associated with that Receive Port and disal-
lows writing to registers. Receive Port A (RxA) in Power-
down mode inhibits access to registers described in Section
18.21 RECEIVE PORT A LINK LABEL — 0x20 RALL to Sec-
tion 18.39 RECEIVE PORT A BIT ERROR COUNT — 0x43
to 0x45 RABEC2 to RABEC0. Receive Port B (RxB) in
Power-down mode inhibits access to registers described in
Section 18.40 RECEIVE PORT B LINK LABEL — 0x60 RBLL
to Section 18.58 RECEIVE PORT B BIT ERROR
COUNT — 0x83 to 0x85 RBBEC2 to RBBEC0. The contents
of these registers are not lost or altered in Power-down
mode.
6.6 PERFORMANCE MONITORING AND ALARMS
The DS92UT16 provides a number of performance metrics
and alarms to assist in equipment/network management.
The programmer can independently enable or disable these
alarms to raise an interrupt. See Section 14.0 Performance
Monitoring for a detailed description of the Performance
Monitoring and General Alarms.
6.7 TEST INTERFACE
The IEEE 1149.1 JTAG [4.] port on the device provides
access to the built-in test features such as boundary SCAN,
Internal SCAN and RAM BIST. It may be used to test the
device individually or as part of a more comprehensive cir-
cuit board or system test. (NOTE: The internal SCAN and
RAM BIST functions are not intended for user access.
Therefore, the device user should never assert the Test_se
pin.)
6.8 LOOPBACKS
To assist in diagnostic testing, the device provides both
LVDS interface loopbacks and ATM cell loopbacks. The
former is suitable for designer or commission testing when
the device is not passing live traffic. The latter allows cell
trace testing on live traffic. The ATM cell loopback operates
by recognizing the user-defined cell header of the special
loopback cells. The available loopback options are shown in
Table 10.
In addition to providing a live round trip test via the cell
loopbacks, the DS92UT16 helps pinpoint failures between
transmit and receive paths by counting the number of loop-
back cells received.
All loopbacks are programmable via the microprocessor
interface.
11 www.national.com
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| PDF Descargar | [ Datasheet DS92UT16TUF.PDF ] | |
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