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PDF IP1203 Data sheet ( Hoja de datos )
| Número de pieza | IP1203 | |
| Descripción | Single Output Full Function Synchronous Buck Power Block | |
| Fabricantes | International Rectifier | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de IP1203 (archivo pdf) en la parte inferior de esta página. Total 23 Páginas | ||
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PD- 96921C
iP1203
www.datasheet4u.com
Features
• 5.5V to 13.2V Input Voltage
• 0.8V to 8V Output Voltage
• 15A Maximum Load Capability
• 200-400kHz Nominal Switching Frequency
• Over Current Hiccup
• External Synchronization Capable
• Overvoltage Protection
• Over Temperature Protection
• Internal Features Minimize Layout Sensitivity
• Very Small Outline 9mm x 9mm x 2.3mm
Single Output Full Function
Synchronous Buck Power Block
Integrated Power Semiconductors,
PWM Control & Passives
iP1203 Power Block
Description
The iP1203 is a fully optimized solution for medium current synchronous buck applications requiring up to 15A.
It includes full function PWM control, with optimized power semiconductor chipsets and associated passives,
achieving high power density. Very few external components are required to create a complete synchronous
buck power supply.
iPOWIR™ technology offers designers an innovative space-saving solution for applications requiring high
power densities. iPOWIR technology eases design for applications where component integration offers benefits
in performance and functionality. iPOWIR technology solutions are also optimized internally for layout, heat
transfer and component selection.
iP1203 Simplified Application Schematic
VIN
VIN OC
VCC_bypass
VSW
FB
PGOOD iP1203
SS
FBS
RT
SYNC
CC
VREF
VOUT
Pin Number
(See Page 18) Pin Name
1, 23
VIN
Pin Description
Input voltage connection pins
2,3,4,5,7,17,20,21 PGND
Power Ground pins
6 VCC_bypass
PWM controller power supply pin. Internally generated.
Requires a 2.2µf external bypass capacitor
8
SS
Soft start pin. External capacitor provides soft start. Pulling soft start pin low
will disable the output. Cannot be cycled to unlatch OVP trip
9 CC
Output of the error amplifier
10 FB
Inverting input of the error amplifier
11 FBs
Output overvoltage sense pin.
12
RT
Switching frequency setting pin. For RT selection, refer to Fig.9 of the
datasheet
13
PGOOD
Power Good pin. Open collector, requires external pulll-up. If function not
needed, pin can be left floating
14
VREF
Non inverting input of the error amplifier (reference Voltage pin). Connect a
100pF cap from this pin to PGND.
15
SYNC
External Clock synchronization pin. Set free running frequency to 80% of
the SYNC frequency. When not in use, leave pin floating
16 OCSET
Output overcurrent trip threshold pin
18,19
22
24
VSW
VSWs
VINs
Output inductor connection pins
Test pad, for internal use, short to VSW
Test pad, for internal use, short to VIN
04/08/05
1 page  
iP1203
6
www.datasheet4u.com
VIN = 12V
VOUT = 1.5V
5 fsw = 300kHz
L = 1.0µH
4 TBLK = 125°C
3
2
Maximum
Typical
1
0
0
5 10
Output Current (A)
Fig. 2: Power Loss vs. Current
15
0
16
Case Temperature (°C)
10 20 30 40 50 60 70 80 90 100 110 120 130
14
12 VIN = 12V
10
VOUT = 1.5V
fsw = 300kHz
8 L = 1.0µH
Safe
Operating
Area
6 Tx
4
2
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130
PCB Temperature (°C)
www.irf.com
Fig. 3: Safe Operating Area (SOA) vs. TPCB & TCASE
5
5 Page 
iP1203
Overcurrent Protection HICCUP
www.Tdahtaeshoevete4ruc.cuormrent protection function of the iP1203
offers a hiccup feature. During overloads, when the
overcurrent trip threshold is reached, the power sup-
ply output shuts down and attempts to restart (out-
put HICCUP mode). The time duration between the
shutdown of the output and the restart is determined
by the time it takes to discharge the soft start ca-
pacitor. Typically, the discharge time of the soft start
capacitor is 10 times the charge time. The duty cycle
of the hiccup process is typically 5%. The output will
stay in hiccup indefinitely until the overload is re-
moved. The typical overcurrent trip threshold of the
device is internally set at 30A. The overcurrent shut-
down / HICCUP threshold is about ±30% accurate.
The iP1203 overcurrent shutdown and HICCUP
threshold can be set externally by adding ROCSET re-
sistor from OCSET pin. Refer to Fig.8 for ROCSET se-
lection.
Overvoltage Protection (OVP)
Overvoltage is sensed through output voltage sense
pin FBs. The OVP threshold is set to 115% of the
output voltage. Upon overvoltage condition, the OVP
forces a latched shutdown. In this mode, the upper
FET turns off and the lower FET turns on, thus
crowbaring the output. Reset is performed by recy-
cling the input voltage. Overvoltage can be sensed
by either connecting FBs to its corresponding output
through a separate output voltage divider resistor
network, or it can be connected directly to its corre-
sponding feedback pin FB. For Type III control loop
compensation, FBs should be connected through
voltage dividers only.
Refer to the iP1203 Design Procedure section on
how to set the OVP trip threshold.
PGOOD
This is an output voltage status signal that is open
collector and is pulled low when the output voltage
falls below 85% of the output voltage. High state in-
dicates that outputs are in regulation. The PGOOD
pin can be left floating if not used.
Thermal Shutdown
The iP1203 provides thermal shutdown. The thresh-
old typically is set to 140°C. When the trip threshold
is exceeded, thermal shutdown turns the output off.
Thermal shutdown is not latched and automatic re-
start is initiated when the sensed temperature drops
to the normal range.
www.irf.com
11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet IP1203.PDF ] | |
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