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PDF ASM3P2759A Data sheet ( Hoja de datos )
| Número de pieza | ASM3P2759A | |
| Descripción | Low Power Peak EMI Reducing Solution | |
| Fabricantes | Alliance Semiconductor Corporation | |
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September 2005
ASM3P2759A
rwewvw1.D.a6taSheet4U.com
Low Power Peak EMI Reducing Solution
Features
Generates an EMI optimized clock signal at the
output.
Integrated loop filter components.
Operates with a 3.3V / 2.5V Supply.
Operating current less than 4mA.
Low power CMOS design.
Input frequency range: 3MHz to 5MHz for 2.5V
: 3MHz to 6MHz for 3.3V
Generates a 1X low EMI spread spectrum clock of
the input frequency.
Frequency deviation: ±1% @ 3MHz
Available in 6-pin TSOT-23, 8-pin SOIC and 8-pin
TSSOP packages.
Product Description
The ASM3P2759A is a versatile spread spectrum
frequency modulator designed specifically for a wide
range of clock frequencies. The ASM3P2759A reduces
electromagnetic interference (EMI) at the clock source,
allowing system wide reduction of EMI of all clock
dependent signals. The ASM3P2759A allows significant
system cost savings by reducing the number of circuit
board layers ferrite beads, shielding that are traditionally
required to pass EMI regulations.
The ASM3P2759A uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented by using a proprietary all digital method.
The ASM3P2759A modulates the output of a single PLL
in order to “spread” the bandwidth of a synthesized clock,
and more importantly, decreases the peak amplitudes of
its harmonics. This results in significantly lower system
EMI compared to the typical narrow band signal produced
by oscillators and most frequency generators. Lowering
EMI by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation’.
Applications
The ASM3P2759A is targeted towards all portable devices
with very low power requirements like MP3 players and
digital still cameras.
Key Specifications
Description
Supply voltages
Cycle-to-Cycle Jitter
Output Duty Cycle
Modulation Rate Equation
Frequency Deviation
Specification
VDD = 3.3V / 2.5V
200pS (Max)
45/55%
FIN/128
±1% @ 3MHz
Block Diagram
VDD
PD
XIN
XOUT
Crystal
Oscillator
Frequency
Divider
Feedback
Divider
Modulation
Phase
Detector
Loop
Filter
PLL
VCO
Output
Divider
ModOUT
VSS
Alliance Semiconductor
2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
1 page  
September 2005
rwewvw1.D.a6taSheet4U.com
DC Electrical Characteristics for 3.3V Supply
(Test condition: All parameters are measured at room temperature (+ 25°C) unless otherwise stated)
Symbol
Parameter
Min
VIL Input low voltage
VIH Input high voltage
VSS - 0.3
2.0
IIL Input low current
IIH Input high current
-
-
IXOL XOUT output low current (@0.4V, VDD=3.3V)
IXOH XOUT output high current (@2.5V, VDD=3.3V)
-
-
VOL Output low voltage (VDD = 3.3 V, IOL = 8mA)
VOH Output high voltage (VDD = 3.3 V, IOH = 8mA)
-
2.5
IDD Static supply current*
ICC Dynamic supply current (3.3V, 3MHz and with no load)
-
-
VDD Operating Voltage
2.7
tON Power-up time (first locked cycle after power-up)**
-
ZOUT Output impedance
-
* XIN/CLKIN and PD pin are pulled low
** VDD and XIN/CLKIN input are stable; PD pin is made high from low.
Typ
-
-
-
-
3
3
-
-
2.5
3.3
-
45
ASM3P2759A
Max
0.8
VDD + 0.3
-35
35
-
-
0.4
-
10
-
3.6
5
-
Unit
V
V
µA
µA
mA
mA
V
V
uA
mA
V
mS
Ω
AC Electrical Characteristics for 3.3V Supply
Symbol
Parameter
CLKIN
Input frequency
ModOUT
Output frequency
fd
Frequency
Deviation
Input Frequency = 3MHz
Input Frequency = 6MHz
tLH* Output rise time (measured from 0.8 to 2.0V)
tHL *
Output fall time (measured at 2.0V to 0.8V)
tJC Jitter (cycle to cycle)
tD Output duty cycle
*tLH and tHL are measured into a capacitive load of 15pF
Min Typ Max Unit
3 - 6 MHz
3 - 6 MHz
- ±1 -
- ±0.55 -
%
0.4 1.0 1.2 nS
0.4 0.9 1.0 nS
- - 200 pS
45 50 55 %
Low Power Peak EMI Reducing Solution
Notice: The information in this document is subject to change without notice.
5 of 12
5 Page 
September 2005
rwewvw1.D.a6taSheet4U.com
Device Ordering Information
ASM3P2759AF-08TR
ASM3P2759A
R = Tape & reel, T = Tube or Tray
O = SOT
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
Q = QFN
DEVICE PIN COUNT
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
D = QSOP
X = SC-70
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE
PART NUMBER
X= Automotive I= Industrial P or n/c = Commercial
(-40C to +125C) (-40C to +85C)
(0C to +70C)
1 = Reserved
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
0 = Reserved
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under U.S Patent Nos 5,488,627 and 5,631,921
Low Power Peak EMI Reducing Solution
Notice: The information in this document is subject to change without notice.
11 of 12
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| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ASM3P2759A.PDF ] | |
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