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What is C8051F066?

This electronic component, produced by the manufacturer "Silicon Laboratories", performs the same function as "(C8051F060 - C8051F067) Mixed Signal ISP Flash MCU Family".


C8051F066 Datasheet PDF - Silicon Laboratories

Part Number C8051F066
Description (C8051F060 - C8051F067) Mixed Signal ISP Flash MCU Family
Manufacturers Silicon Laboratories 
Logo Silicon Laboratories Logo 


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C8051F060/1/2/3/4/5/6/7
Mixed Signal ISP Flash MCU Family
Analog Peripherals
- Two 16-Bit SAR ADCs
16-bit resolution
±0.75 LSB INL, guaranteed no missing codes
Programmable throughput up to 1 Msps
Operate as two single-ended or one differential con-
verter
Direct memory access; data stored in RAM without
software overhead
Data-dependent windowed interrupt generator
- 10-bit SAR ADC (C8051F060/1/2/3)
Programmable throughput up to 200 ksps
www.DataSheet4U.com 8 external inputs, single-ended or differential
Built-in temperature sensor
- Two 12-bit DACs (C8051F060/1/2/3)
Can synchronize outputs to timers for jitter-free wave-
form generation
- Three Analog Comparators
Programmable hysteresis/response time
- Voltage Reference
- Precision VDD Monitor/Brown-Out Detector
On-Chip JTAG Debug & Boundary Scan
- On-chip debug circuitry facilitates full-speed, non-
intrusive in-circuit/in-system debugging
- Provides breakpoints, single-stepping, watchpoints,
stack monitor; inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- IEEE1149.1 compliant boundary scan
- Complete development kit
High Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instruction set in 1 or 2 system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- Flexible Interrupt sources
Memory
- 4352 Bytes internal data RAM (4 k + 256)
- 64 kB (C8051F060/1/2/3/4/5), 32 kB (C8051F066/7)
Flash; In-system programmable in 512-byte sectors
- External 64 kB data memory interface with multi-
plexed and non-multiplexed modes (C8051F060/2/
4/6)
Digital Peripherals
- 59 general purpose I/O pins (C8051F060/2/4/6)
- 24 general purpose I/O pins (C8051F061/3/5/7)
- Bosch Controller Area Network (CAN 2.0B -
C8051F060/1/2/3)
- Hardware SMBus™ (I2C™ Compatible), SPI™, and
two UART serial ports available concurrently
- Programmable 16-bit counter/timer array with
6 capture/compare modules
- 5 general purpose 16-bit counter/timers
- Dedicated watchdog timer; bi-directional reset pin
Clock Sources
- Internal calibrated precision oscillator: 24.5 MHz
- External oscillator: Crystal, RC, C, or clock
Supply Voltage .......................... 2.7 to 3.6 V
- Multiple power saving sleep and shutdown modes
100-Pin and 64-Pin TQFP Packages Available
Temperature Range: -40 to +85 °C
ANALOGPERIPHERALS
16-bit
1 Msps
ADC
16-bit
1 Msps
ADC
DMA
Interface
VREF
+ ++
- --
VOLTAGE
COMPARATOR
S
10-bit
200ksps
ADC
TEMP
SENSOR
C8051F060/1/2/3Only
12-Bit
DAC
12-Bit
DAC
DIGITAL I/O
CAN 2.0B
C8051F060/1/2/3
Port 0
Port 1
UART0
UART1
SMBus
SPI Bus
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
100 pin Only
HIGH-SPEED CONTROLLER CORE
8051 CPU
(25MIPS)
22
INTERRUPTS
64/32 kB
ISP FLASH
DEBUG
CIRCUITRY
4352 B
SRAM
JTAG
CLOCK
SANITY
CIRCUIT CONTROL
Preliminary Rev. 1.2 7/04
Copyright © 2004 by Silicon Laboratories
C8051F060/1/2/3/4/5/6/7
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

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C8051F066 equivalent
C8051F060/1/2/3/4/5/6/7
14.7.1.Enable/Reset WDT ................................................................................ 166
14.7.2.Disable WDT .......................................................................................... 166
14.7.3.Disable WDT Lockout ............................................................................ 166
14.7.4.Setting WDT Interval .............................................................................. 166
15. Oscillators ............................................................................................................. 171
15.1.Programmable Internal Oscillator ................................................................... 171
15.2.External Oscillator Drive Circuit...................................................................... 173
15.3.System Clock Selection.................................................................................. 173
15.4.External Crystal Example ............................................................................... 175
15.5.External RC Example ..................................................................................... 175
www.DataSheet4U.com 15.6.External Capacitor Example ........................................................................... 175
16. Flash Memory ....................................................................................................... 177
16.1.Programming The Flash Memory ................................................................... 177
16.2.Non-volatile Data Storage .............................................................................. 178
16.3.Security Options ............................................................................................. 179
16.3.1.Summary of Flash Security Options....................................................... 183
17. External Data Memory Interface and On-Chip XRAM........................................ 187
17.1.Accessing XRAM............................................................................................ 187
17.1.1.16-Bit MOVX Example ........................................................................... 187
17.1.2.8-Bit MOVX Example ............................................................................. 187
17.2.Configuring the External Memory Interface .................................................... 188
17.3.Port Selection and Configuration.................................................................... 188
17.4.Multiplexed and Non-multiplexed Selection.................................................... 190
17.4.1.Multiplexed Configuration....................................................................... 190
17.4.2.Non-multiplexed Configuration............................................................... 191
17.5.Memory Mode Selection................................................................................. 192
17.5.1.Internal XRAM Only ............................................................................... 192
17.5.2.Split Mode without Bank Select.............................................................. 192
17.5.3.Split Mode with Bank Select................................................................... 193
17.5.4.External Only.......................................................................................... 193
17.6.Timing .......................................................................................................... 194
17.6.1.Non-multiplexed Mode ........................................................................... 196
17.6.1.1.16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or ‘111’......................... 196
17.6.1.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or ‘111’..... 197
17.6.1.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘110’....................... 198
17.6.2.Multiplexed Mode ................................................................................... 199
17.6.2.1.16-bit MOVX: EMI0CF[4:2] = ‘001’, ‘010’, or ‘011’......................... 199
17.6.2.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘001’ or ‘011’..... 200
17.6.2.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘010’....................... 201
18. Port Input/Output.................................................................................................. 203
18.1.Ports 0 through 3 and the Priority Crossbar Decoder..................................... 205
18.1.1.Crossbar Pin Assignment and Allocation ............................................... 205
18.1.2.Configuring the Output Modes of the Port Pins...................................... 206
18.1.3.Configuring Port Pins as Digital Inputs................................................... 207
18.1.4.Weak Pull-ups ........................................................................................ 207
Rev. 1.2
5


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