1GW3B2AN6 Datasheet PDF - ST Microelectronics
Part Number | 1GW3B2AN6 | |
Description | NAND Flash Memory | |
Manufacturers | ST Microelectronics | |
Logo | ||
There is a preview and 1GW3B2AN6 download ( pdf file ) link at the bottom of this page. Total 30 Pages |
Preview 1 page No Preview Available ! NAND512-B, NAND01G-B NAND02G-B
NAND04G-B NAND08G-B
512 Mbit, 1 Gbit, 2 Gbit, 4 Gbit, 8 Gbit
2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory
PRELIMINARY DATA
FEATURES SUMMARY
■ HIGH DENSITY NAND FLASH MEMORIES
www.DataSheet4U.com
– Up to 8 Gbit memory array
– Up to 64Mbit spare area
– Cost effective solutions for mass storage
applications
■ NAND INTERFACE
– x8 or x16 bus width
– Multiplexed Address/ Data
– Pinout compatibility for all densities
■ SUPPLY VOLTAGE
– 1.8V device: VDD = 1.7 to 1.95V
– 3.0V device: VDD = 2.7 to 3.6V
■ PAGE SIZE
– x8 device: (2048 + 64 spare) Bytes
– x16 device: (1024 + 32 spare) Words
■ BLOCK SIZE
– x8 device: (128K + 4K spare) Bytes
– x16 device: (64K + 2K spare) Words
■ PAGE READ / PROGRAM
– Random access: 25µs (max)
– Sequential access: 50ns (min)
– Page program time: 300µs (typ)
■ COPY BACK PROGRAM MODE
– Fast page copy without external buffering
■ CACHE PROGRAM AND CACHE READ
MODES
– Internal Cache Register to improve the
program and read throughputs
■ FAST BLOCK ERASE
– Block erase time: 2ms (typ)
■ STATUS REGISTER
■ ELECTRONIC SIGNATURE
■ CHIP ENABLE ‘DON’T CARE’
– for simple interface with microcontroller
■ AUTOMATIC PAGE 0 READ AT POWER-UP
– Boot from NAND support
■ SERIAL NUMBER OPTION
Figure 1. Packages
TSOP48 12 x 20mm
USOP48 12 x 17 x 0.65mm
FBGA
VFBGA63 9.5 x 12 x 1mm
TFBGA63 9.5 x 12 x 1.2mm
LFBGA63 9.5 x 12 x 1.4mm
■ DATA PROTECTION
– Hardware and Software Block Locking
– Hardware Program/Erase locked during
Power transitions
■ DATA INTEGRITY
– 100,000 Program/Erase cycles
– 10 years Data Retention
■ RoHS COMPLIANCE
– Lead-Free Components are Compliant
with the RoHS Directive
■ DEVELOPMENT TOOLS
– Error Correction Code software and
hardware models
– Bad Blocks Management and Wear
Leveling algorithms
– PC Demo board with simulation software
– File System OS Native reference software
– Hardware simulation models
February 2005
1/59
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Blocks Unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 19.Blocks Unlock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Blocks Lock-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 20.Read Block Lock Status Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 16. Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 21.Block Protection State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
SOFTWARE ALGORITHMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
www.DataSheet4U.comBad Block Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Block Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 17. Block Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 22.Bad Block Management Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 23.Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Wear-leveling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Error Correction Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 24.Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Hardware Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 18. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 39
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 19. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 20. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 21. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 22. DC Characteristics, 1.8V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 23. DC Characteristics, 3V Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 24. AC Characteristics for Command, Address, Data Input . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 25. AC Characteristics for Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 25.Command Latch AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 26.Address Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 27.Data Input Latch AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 28.Sequential Data Output after Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 29.Read Status Register AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 30.Read Electronic Signature AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 31.Page Read Operation AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 32.Page Program AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 33.Block Erase AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 34.Reset AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Ready/Busy Signal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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Information | Total 30 Pages | |
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