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What is CY14E256L?

This electronic component, produced by the manufacturer "Cypress Semiconductor", performs the same function as "256-Kbit (32K x 8) nvSRAM".


CY14E256L Datasheet PDF - Cypress Semiconductor

Part Number CY14E256L
Description 256-Kbit (32K x 8) nvSRAM
Manufacturers Cypress Semiconductor 
Logo Cypress Semiconductor Logo 


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PRELIMINARY
CY14E256L
256-Kbit (32K x 8) nvSRAM
Features
• 25 ns and 45 ns Access Times
• “Hands-off” Automatic STORE on Power Down with
external 68µF capacitor
STORE to QuantumTrap® Nonvolatile Elements is
initiated by Software, Hardware or Autostore® on
www.DataSheet4UP.coowmer-down
RECALL to SRAM Initiated by Software or Power-up
• Infinite READ, WRITE and RECALL Cycles
• 15 mA Typical ICC at 200 ns Cycle Time
• 1,000,000 STORE Cycles to QuantumTrap
• 100-Year Data Retention to QuantumTrap
• Single 5V Operation +10%
• Commercial Temperature
• SOIC Package
• RoHS Compliance
Functional Description
The Cypress CY14E256L is a fast static RAM with a nonvol-
atile element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
Infinite read and write cycles, while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down.
On power-up, data is restored to the SRAM (the RECALL
operation) from the nonvolatile memory. Both the STORE and
RECALL operations are also available under software control.
A hardware STORE may be initiated with HSB pin.
Logic Block Diagram
Quantum Trap
VCC
VCAP
512 X 512
A5
STORE
POWER
CONTROL
A6
A7
A8
A9
A 11
A 12
STATIC RAM
ARRAY
512 X 512
RECALL
STORE/
RECALL
CONTROL
HSB
A 13
A14 SOFTWARE
-DETECT
A13 A0
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
OE
CE
WE
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709
• 408-943-2600
Document #: 001-06968 Rev. *C
Revised November 28, 2006
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CY14E256L equivalent
PRELIMINARY
CY14E256L
The software sequence may be clocked with CE-controlled
READs or OE-controlled READs. Once the sixth address in
the sequence has been entered, the STORE cycle will
commence and the chip will be disabled. It is important that
READ cycles and not WRITE cycles be used in the sequence,
although it is not necessary that OE be low for the sequence
to be valid. After the tSTORE cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE operation.
Software RECALL
Data can be transferred from the nonvolatile memory to the
SRAM by a software address sequence. A software RECALL
cycle is initiated with a sequence of READ operations in a
manner similar to the software STORE initiation. To initiate the
www.DataSheetR4UE.CcoAmLL cycle, the following sequence of CE-controlled
READ operations must be performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0C63, Initiate RECALL cycle
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared, and second, the nonvolatile information is
transferred into the SRAM cells. After the tRECALL cycle time
the SRAM will once again be ready for READ and WRITE
operations. The RECALL operation in no way alters the data
in the nonvolatile elements.
Data Protection
The CY14E256L protects data from corruption during
low-voltage conditions by inhibiting all externally initiated
STORE and WRITE operations. The low voltage condition is
detected when VCC < VSWITCH. If the CY14E256L is in a
WRITE mode (both CE and WE low) at power-up, after a
RECALL, or after a STORE, the WRITE will be inhibited until
a negative transition on CE or WE is detected. This protects
against inadvertent writes during power-up or brown-out
conditions.
Noise Considerations
Figure 4. Current vs. Cycle Time (READ)
Figure 5. Current vs. Cycle Time (WRITE)
ICC and READ/WRITE cycle time. Worst-case current
consumption is shown for both CMOS and TTL input levels
(commercial temperature range, VCC = 5.5V, 100% duty cycle
on chip enable).Only standby current is drawn when the chip
is disabled. The overall average current drawn by the
CY14E256L depends on the following items:
1. The duty cycle of chip enable.
2. The overall cycle rate for accesses.
3. The ratio of READs to WRITEs.
4. CMOS vs. TTL Input Levels.
5. The operating temperature.
6. The VCC level.
7. I/O loading.
The CY14E256L is a high-speed memory and so must have a
high-frequency bypass capacitor of approximately 0.1 µF
connected between VCC and VSS, using leads and traces that
are as short as possible. As with all high-speed CMOS ICs,
careful routing of power, ground, and signals will reduce circuit
noise.
Low Average Active Power
CMOS technology provides the CY14E256L the benefit of
drawing significantly less current when it is cycled at times
longer than 50 ns. Figure 4 shows the relationship between
Table 1. Hardware Mode Selection
Preventing STOREs
The STORE function can be disabled on the fly by holding HSB
high with a driver capable of sourcing 30 mA at a VOH of at
least 2.2V, as it will have to overpower the internal pull-down
device that drives HSB low for 20 µs at the onset of a STORE.
When the CY14E256L is connected for AutoStore operation
(system VCC connected to VCC and a 68-µF capacitor on
VCAP) and VCC crosses VSWITCH on the way down, the
CY14E256L will attempt to pull HSB low; if HSB doesn’t
actually get below VIL,the part will stop trying to pull HSB low
and abort the STORE attempt.
CE WE
HX
LH
LL
XX
Document #: 001-06968 Rev. *C
HSB
H
H
H
L
A13–A0
X
X
X
X
Mode
Not Selected
Read SRAM
Write SRAM
Nonvolatile STORE
I/O
Output High-Z
Output Data
Input Data
Output High-Z
Power
Standby
Active
Active
ICC2
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