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PDF CY14B256K Data sheet ( Hoja de datos )
| Número de pieza | CY14B256K | |
| Descripción | 256-Kbit (32K x 8) nvSRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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PRELIMINARY
CY14B256K
256-Kbit (32K x 8) nvSRAM with Real-Time-Clock
Features
• Data integrity of Cypress nvSRAM combined with full
featured real time clock
— Low power, 300 nA Max, RTC current
— Capacitor or battery backup for RTC
• Watchdog timer
www.DataSheet•4UC.cloocmk alarm with programmable interrupts
• 25 ns, 35 ns, and 45 ns access times
• “Hands-off” automatic STORE on power down with only a
small capacitor
• STORE to QuantumTrap™ initiated by software, device pin,
or on power down
• RECALL to SRAM initiated by software or on power up
• Infinite READ, WRITE, and RECALL cycles
• High reliability
— Endurance to 200K cycles
— Data retention: 20 years @ 55°C
• 10 mA typical ICC at 200 ns cycle time
• Single 3V operation with tolerance of +15%, -10%
• Commercial and industrial temperature
• SSOP Package (ROHS compliant)
Logic Block Diagram
Functional Description
The Cypress CY14B256K combines a 256 Kbit nonvolatile
static RAM with a full featured real-time-clock in a monolithic
integrated circuit. The embedded nonvolatile elements
incorporate QuantumTrap technology producing the world’s
most reliable nonvolatile memory. The SRAM can be read and
written an infinite number of times, while independent,
nonvolatile data resides in the nonvolatile elements.
The real-time-clock function provides an accurate clock with
leap year tracking and a programmable, high accuracy
oscillator. The alarm function is programmable for one time
alarms or periodic seconds, minutes, hours, or days. There is
also a programmable watchdog timer for process control.
QuantumTrap
VCC
VCAP
512 X 512
POWER
VRTCbat
A5
STORE
CONTROL
VRTCcap
A6
A7
A8
A9
STATIC RAM
ARRAY
RECALL
STORE/
RECALL
CONTROL
HSB
A11 512 X 512
A 12
A 13
-A 14
SOFTWARE
DETECT
A13 A0
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
COLUMN IO
COLUMN DEC
A0 A1 A2 A3 A4 A10
RTC
MUX
x1
x2
INT
-A14 A0
OE
CE
WE
Cypress Semiconductor Corporation
Document Number: 001-06431 Rev. *E
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised January 29, 2007
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PRELIMINARY
CY14B256K
Noise Considerations
The CY14B256K is a high-speed memory and so must have
a high-frequency bypass capacitor of approximately 0.1 µF
connected between VCC and VSS, using leads and traces that
are as short as possible. As with all high speed CMOS ICs,
careful routing of power, ground, and signals will reduce circuit
noise.
Low Average Active Power
CMOS technology provides CY14B256K which allows
drawing less current when it is cycled at times longer than 50
www.DataSheetn4sU..cFoimgure 2 shows the relationship between ICC and READ
and/or WRITE cycle time. Worst case current consumption is
shown for commercial temperature range, VCC = 3.45V, and
chip enable at maximum frequency. Only standby current is
drawn when the chip is disabled. The overall average current
drawn by the CY14B256K depends on the following items:
1. 1The duty cycle of chip enable.
2. The overall cycle rate for accesses.
3. The ratio of READs to WRITEs.
4. The operating temperature.
5. The VCC level.
6. IO loading.
Figure 2. Current vs. Cycle Time
Real-Time-Clock Operation
nvTIME Operation
The CY14B256K consists of internal registers that contain
clock, alarm, watchdog, interrupt, and control functions.
Internal double buffering of the clock and the clock/timer
information registers prevents accessing transitional internal
clock data during a read or write operation. Double buffering
also circumvents disrupting normal timing counts or clock
accuracy of the internal clock while accessing clock data.
Clock and Alarm Registers store data in BCD format.
Clock Operations
The clock registers maintain time up to 9,999 years in one
second increments. The user can set the time to any calendar
time and the clock automatically keeps track of days of the
week and month, leap years, and century transitions. There
are eight registers dedicated to the clock functions that are
used to set time with a write cycle and to read time during a
read cycle. These registers contain the time of day in BCD
format. Bits defined as 0 are currently not used and are
reserved for future use by Cypress.
Reading the Clock
While the double buffered RTC register structure reduces the
chance of reading incorrect data from the clock, you to halt
internal updates to the CY14B256K clock registers before
reading clock data to prevent the reading of data in transition.
Stopping the internal register updates does not affect clock
accuracy. The update process is stopped by writing a 1 to the
read bit R (in the flags register at 0x7FF0), and will not restart
until a 0 is written to the read bit. The RTC registers can then
be read while the internal clock continues to run. Within 20 ms
after a 0 is written to the read bit, all CY14B256K registers are
simultaneously updated.
Setting the Clock
Setting the write bit W (in the flags register at 0x7FF0) to a 1
stops updates to the CY14B256K registers. The correct day,
date, and time can then be written into the registers in 24 hour
BCD format. The time written is referred to as the Base Time.
This value is stored in nonvolatile registers and used in
calculation of the current time. Resetting the write bit to 0
transfers those values to the actual clock counters, after which
the clock resumes normal operation.
Backup Power
The RTC in the CY14B256K is used for permanently powered
operation. Either the VRTCcap or VRTCbat pin is connected
depending on whether a capacitor or battery is chosen for the
application. When primary power, VCC, fails and drops below
VSWITCH the device will switch to the backup power supply.
The clock oscillator uses very little current, which maximizes
the backup time available from the backup source. Regardless
of clock operation with the primary source removed, the data
stored in nvSRAM is secure, having been stored in the
nonvolatile elements as power was lost.
During backup operation the CY14B256K consumes a
maximum of 300 nA at 2V. Capacitor or battery values must
be chosen according to the application. Backup time values
based on maximum current specs are shown in Table 2, RTC
Backup Time. Nominal times are approximately 3 times longer.
Table 2. RTC Backup Time
Capacitor Value
0.1F
0.47F
1.0F
Backup Time
72 hours
14 days
30 days
Using a capacitor has the advantage of recharging the backup
source each time the system is powered up. If a battery is
used, a 3V lithium is recommended and the CY14B256K will
Document Number: 001-06431 Rev. *E
Page 5 of 23
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PRELIMINARY
CY14B256K
Table 4. Register Map Detail (continued)
0x7FF6
WIE
AIE
PFIE
www.DataSheet4U.cHom/L
P/L
0x7FF5
M
0x7FF4
M
0x7FF3
M
0x7FF2
M
0x7FF1
Interrupt Status/Control
D7 D6
D5
D4 D3 D2 D1 D0
WIE AIE
PFIE
0
H/L P/L
0
0
Watchdog Interrupt Enable. When set to 1 and a watchdog time-out occurs, the watchdog timer drives the INT pin
as well as the WDF flag. When set to 0, the watchdog time-out affects only the WDF flag.
Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin as well as the AF flag. When set to 0, the
alarm match only affects the AF flag.
Power Fail Enable. When set to 1, the alarm match drives the INT pin as well as the PF flag. When set to 0, the
power fail monitor affects only the PF flag.
High/Low. When set to a 1, the INT pin is driven active HIGH. When set to 0, the INT pin is open drain, active LOW.
Pulse/Level. When set to a 1, the INT pin is driven active (determined by H/L) by an interrupt source for approximately
200 ms. When set to a 0, the INT pin is driven to an active level (as set by H/L) until the Flags/Control register is read.
Alarm - Day
D7 D6
D5
D4 D3 D2 D1 D0
M0
10s Alarm Date
Alarm Date
Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.
Match. Setting this bit to 0 causes the date value to be used in the alarm match. Setting this bit to 1 causes the match
circuit to ignore the date value.
Alarm - Hours
D7 D6
D5
D4 D3 D2 D1 D0
M0
10s Alarm Hours
Alarm Hours
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
Match. Setting this bit to 0 causes the hours value to be used in the alarm match. Setting this bit to 1 causes the
match circuit to ignore the hours value.
Alarm - Minutes
D7 D6
D5
D4 D3 D2 D1 D0
M 0 10s Alarm Minutes
Alarm Minutes
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.
Match. Setting this bit to 0 causes the minutes value to be used in the alarm match. Setting this bit to 1 causes the
match circuit to ignore the minutes value.
Alarm - Seconds
D7 D6
D5
D4 D3 D2 D1 D0
M 0 10s Alarm Seconds
Alarm Seconds
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value.
Match. Setting this bit to 0 causes the seconds’ value to be used in the alarm match. Setting this bit to 1 causes the
match circuit to ignore the seconds value.
Time Keeping - Centuries
D7 D6
D5
D4 D3 D2 D1 D0
00
10s Centuries
Centuries
Document Number: 001-06431 Rev. *E
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| PDF Descargar | [ Datasheet CY14B256K.PDF ] | |
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