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PDF ICS1893CY-10 Data sheet ( Hoja de datos )
| Número de pieza | ICS1893CY-10 | |
| Descripción | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated Device Technology, Inc.
ICS1893CY-10
Document Type: Data Sheet
Document Stage: Preliminary Release
3.3-V 10Base-T/100Base-TX Integrated PHYceiver™
General
The ICS1893CY-10 is a low-power, physical-layer device
(PHY) that supports the ISO/IEC 10Base-T and 100Base-TX
Carrier-Sense Multiple Access/Collision Detection
(CSMA/CD) Ethernet standards. The ICS1893CY-10
supports managed or unmanaged node, repeater, and
switch applications.
www.DataSheeTt4hUe.cIoCmS1893CY-10 is intended for MII, Node applications
that require the Auto-MIDIX feature that automatically
corrects crossover errors in plant wiring.
The ICS1893CY-10 incorporates digital signal processing
(DSP) in its Physical Medium Dependent (PMD) sublayer.
As a result, it can transmit and receive data on unshielded
twisted-pair (UTP) category 5 cables with attenuation in
excess of 24 dB at 100 MHz. With this ICS-patented
technology, the ICS1893CY-10 can virtually eliminate errors
from killer packets.
The ICS1893CY-10 provides a Serial Management Interface
for exchanging command and status information with a
Station Management (STA) entity.
The ICS1893CY-10 Media Dependent Interface (MDI) can
be configured to provide either half- or full-duplex operation
at data rates of 10 MHz or 100 MHz. The MDI configuration
can be established manually (with input pins or control
register settings) or automatically (using the
Auto-Negotiation features). When the ICS1893CY-10
Auto-Negotiation sublayer is enabled, it exchanges
technology capability data with its remote link partner and
automatically selects the highest-performance operating
mode they have in common.
Features
• Supports category 5 cables with attenuation in excess of
24 dB at 100 MHz
• Fully integrated, DSP-based PMD includes:
– Adaptive equalization and baseline wander correction
– Transmit wave shaping and stream cipher scrambler
– MLT-3 encoder and NRZ/NRZI encoder
• Low-power, 0.35-micron CMOS (typically 400 mW)
• Power-down mode typically 21mW
• Single 3.3-V power supply.
• Single-chip, fully integrated PHY provides PCS, PMA,
PMD, and AUTONEG sublayers of IEEE standard
• 10Base-T and 100Base-TX IEEE 802.3 compliant
• Highly configurable design supports:
– Node, repeater, and switch applications
– Managed and unmanaged applications
– 10M or 100M half- and full-duplex modes
– Parallel detection
– Auto-negotiation, with Next Page capabilities
– Auto-MDI/MDIX crossover correction
• MAC/Repeater Interface can be configured as:
– 10M or 100M Media Independent Interface
– 100M Symbol Interface (bypasses the PCS)
– 10M 7-wire Serial Interface
• Clock and crystal supported
• Small Footprint 64-pin Thin Quad Flat Pack (TQFP)
• Available in Industrial Temperature and Lead-Free
ICS1893CY-10 Block Diagram
10/100 MII or
Alternate
MAC/Repeater
Interface
Interface
MUX
PCS
• Frame
• CRS/COL
Detection
• Parallel to Serial
• 4B/5B
MII Serial
Management
Interface
MII
Extended
Register
Set
Low-Jitter
Clock
Synthesizer
Clock
100Base-T
PMA
• Clock Recovery
• Link Monitor
• Signal Detection
• Error Detection
10Base-T
TP_PMD
• MLT-3
• Stream Cipher
• Adaptive Equalizer
• Baseline Wander
Correction
Configuration
and Status
Integrated
Switch
Auto-
Negotiation
Twisted-
Pair
Interface to
Magnetics
Modules and
RJ45
Connector
Power
LEDs and PHY
Address
ICS1893CY-10
Rev 1/07
IDT reserves the right to make changes in the device data identified in
this publication without further notice. IDT advises its customers to
obtain the latest version of all device data to verify that any information
being relied upon by the customer is current and accurate.
1 page  
ICS1893CY-10 - Release
Table of Contents
Table of Contents
Section
7.5
7.5.1
7.5.2
7.5.3
7.6
www.DataSheet4U.com 7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
7.6.6
7.7
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.8
7.8.1
7.8.2
7.8.3
7.8.4
7.8.5
7.8.6
7.9
7.9.1
7.9.2
7.9.3
7.9.4
7.9.5
7.9.6
7.10
7.10.1
7.10.2
7.10.3
7.10.4
7.10.5
Title
Page
Register 3: PHY Identifier Register ........................................................................71
OUI bits 19-24 (bits 3.15:10) ..................................................................................71
Manufacturer’s Model Number (bits 3.9:4) .............................................................71
Revision Number (bits 3.3:0) .................................................................................72
Register 4: Auto-Negotiation Register ...................................................................72
Next Page (bit 4.15) ...............................................................................................73
IEEE Reserved Bit (bit 4.14) ..................................................................................73
Remote Fault (bit 4.13) ..........................................................................................73
IEEE Reserved Bits (bits 4.12:10) .........................................................................73
Technology Ability Field (bits 4.9:5) .......................................................................74
Selector Field (Bits 4.4:0)........................................................................................75
Register 5: Auto-Negotiation Link Partner Ability Register ....................................76
Next Page (bit 5.15) ...............................................................................................76
Acknowledge (bit 5.14) ..........................................................................................77
Remote Fault (bit 5.13) ..........................................................................................77
Technology Ability Field (bits 5.12:5) .....................................................................77
Selector Field (bits 5.4:0) .......................................................................................77
Register 6: Auto-Negotiation Expansion Register ..................................................78
IEEE Reserved Bits (bits 6.15:5) ...........................................................................78
Parallel Detection Fault (bit 6.4) .............................................................................79
Link Partner Next Page Able (bit 6.3) ....................................................................79
Next Page Able (bit 6.2) .........................................................................................79
Page Received (bit 6.1) .........................................................................................79
Link Partner Auto-Negotiation Able (bit 6.0) ..........................................................79
Register 7: Auto-Negotiation Next Page Transmit Register ...................................80
Next Page (bit 7.15) ...............................................................................................81
IEEE Reserved Bit (bit 7.14) ..................................................................................81
Message Page (bit 7.13) ........................................................................................81
Acknowledge 2 (bit 7.12) .......................................................................................81
Toggle (bit 7.11) .....................................................................................................81
Message Code Field / Unformatted Code Field (bits 7.10:0) .................................81
Register 8: Auto-Negotiation Next Page Link Partner Ability Register ...................82
Next Page (bit 8.15) ...............................................................................................83
IEEE Reserved Bit (bit 8.14) ..................................................................................83
Message Page (bit 8.13) ........................................................................................83
Acknowledge 2 (bit 8.12) .......................................................................................83
Message Code Field / Unformatted Code Field (bits 8.10:0) .................................83
ICS1893CY-10 Rev 1/07
Copyright © 2007, Integrated Device Technology, Inc.
All rights reserved.
5
5 Page 
ICS1893CY-10 - Release
Chapter 1 Abbreviations and Acronyms
Table 1-1. Abbreviations and Acronyms (Continued)
Abbreviation /
Acronym
Interpretation
OUI Organizationally Unique Identifier
PCS
Physical Coding sublayer
PHY
The ICS1893CY-10 is a physical-layer device, also referred to as a ‘PHY’ or
‘PHYceiver’.
PLL phase-locked loop
PMA
Physical Medium Attachment
PMD
www.DataSheet4U.com ppm
Physical Medium Dependent
parts per million
QFP
quad flat pack
RO read only
R/W
read/write
R/W0
read/write zero
SC self-clearing
SF Special Functions
SFD
Start-of-Frame Delimiter
SI Stream Interface, Serial Interface, or Symbol Interface.
With reference to the MII/SI pin, the acronym ‘SI’ has multiple meanings.
• Generically, SI means ’Stream Interface’, and is documented as such in this data
sheet.
• However, when the MAC/Repeater Interface is configured for:
– 10M operations, SI is an acronym for 'Serial Interface'.
– 100M operations, SI is an acronym for 'Symbol Interface'.
SQE
Signal Quality Error
SSD
Start-of-Stream Delimiter
STA Station Management Entity
STP shielded twisted pair
TAF Technology Ability Field
TP-PMD
Twisted-Pair Physical Layer Medium Dependent
Typ. typical
UTP
unshielded twisted pair
ICS1893CY-10 Rev 1/07
Copyright © 2007, Integrated Device Technology, Inc.
All rights reserved.
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