79RC32438 Datasheet PDF - Integrated Device Technology
Part Number | 79RC32438 | |
Description | IDTTM InterpriseTM Integrated Communications Processor | |
Manufacturers | Integrated Device Technology | |
Logo | ||
There is a preview and 79RC32438 download ( pdf file ) link at the bottom of this page. Total 30 Pages |
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Communications Processor
79RC32438
Features
◆ 32-bit CPU Core
– MIPS32 instruction set
– Cache Sizes: 16KB instruction and data caches, 4-Way set
associative, cache line locking, non-blocking prefetches
– 16 dual-entry JTLB with variable page sizes
– 3-entry instruction TLB
www.DataSheet4–U.c3o-mentry data TLB
– Max issue rate of one 32x16 multiply per clock
– Max issue rate of one 32x32 multiply every other clock
– CPU control with start, stop and single stepping
– Software breakpoints support
– Hardware breakpoints on virtual addresses
– Enhanced JTAG and ICE Interface that is compatible with v2.5
of the EJTAG Specification
◆ DDR Memory Controller
– Supports up to 2GB of DDR SDRAM
– 2 chip selects (each chip select supports 4 internal DDR
banks)
– Supports 16-bit or 32-bit data bus width using 8, 16, or 32-bit
devices
– Supports 64Mb, 128Mb, 256Mb, 512Mb, and 1Gb DDR
SDRAM devices
– Data bus multiplexing support allows interfacing to standard
DDR DIMMs and SODIMMs
– Automatic refresh generation
◆ Memory and Peripheral Device Controller
– Provides “glueless” interface to standard SRAM, Flash, ROM,
dual-port memory, and peripheral devices
– Demultiplexed address and data buses: 16-bit data bus, 26-bit
address bus, 6 chip selects, supports alternate bus masters,
control for external data bus buffers
– Supports 8-bit and 16-bit width devices
Automatic byte gathering and scattering
– Flexible protocol configuration parameters: programmable
number of wait states (0 to 63), programmable postread/post-
write delay (0 to 31), supports external wait state generation,
supports Intel and Motorola style peripherals
– Write protect capability per chip select
– Programmable bus transaction timer generates warm reset
when counter expires
– Supports up to 64 MB of memory per chip select
◆ Counter/Timers
– Three general purpose 32-bit counter timers
◆ PCI Interface
– 32-bit PCI revision 2.2 compliant (3.3V only)
– Supports host or satellite operation in both master and target
modes
– Support for synchronous and asynchronous operation
– PCI clock supports frequencies from 16 MHz to 66 MHz
– PCI arbiter in Host mode: supports 6 external masters, fixed
priority or round robin arbitration
– I2O “like” PCI Messaging Unit
Block Diagram
MII MII
MIPS-32
CPU Core
Interrupt
Controller
:
:
2 Ethernet
ICE
EJTAG
MMU
D. Cache I. Cache
3 Counter
Timers
10/100
Interfaces
DDR &
DDR
Device
Controllers
IPBusTM
On-Chip
Memory
DMA
Controller
Arbiter
I2C
Controller
2 UARTS
(16550)
GPIO
Interface
SPI
Controller
PCI
Master/Target
Interface
PCI Arbiter
(Host Mode)
Memory & I2C Bus
Peripheral Bus
Ch. 1 Ch. 2
Serial Channels
GPIO Pins SPI Bus
PCI Bus
© 2004 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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May 25, 2004
DSC 6148
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IDT 79RC32438
www.DataSheet4U.com
Signal
WAITACKN
DDR Bus
DDRADDR[13:0]
DDRBA[1:0]
DDRCASN
DDRCKE
DDRCKN[1:0]
DDRCKP[1:0]
DDRCSN[1:0]
DDRDATA[31:0]
DDRDM[7:0]
DDRDQS[3:0]
DDROEN[3:0]
DDRRASN
Type
I
Name/Description
Wait or Transfer Acknowledge. When configured as wait, this signal is
asserted during a memory and peripheral bus transaction to extend the bus
cycle. When configured as a transfer acknowledge, this signal is asserted during
a transaction to signal the completion of the transaction.
O DDR Address Bus. 14-bit multiplexed DDR bus address bus. This bus is used
to transfer the addresses to the DDR devices.
O DDR Bank Address. These signals are used to transfer the bank address to the
DDRs.
O DDR Column Address Strobe. This signal is asserted during DDR transac-
tions.
O DDR Clock Enable. The DDR clock enable is asserted during normal DDR
operation. This signal is negated during following a cold reset or during a power
down operation.
O DDR Negative DDR clock. These signals are the negative clock of the differen-
tial DDR clock pair. Two copies of this output are provided to reduce signal load-
ing.
O DDR Positive DDR clock. These signals are the positive clock of the differen-
tial DDR clock pair. Two copies of this output are provided to reduce signal load-
ing.
O DDR Chip Selects. These active low signals are used to select DDR device(s)
on the DDR bus.
I/O DDR Data Bus. 32-bit DDR data bus used to transfer data between the
RC32438 and the DDR devices. Data is transferred on both edges of the clock.
O DDR Data Write Enables. Byte data write enables used to enable specific byte
lanes during DDR writes.
DDRDM[0] corresponds to DDRDATA[7:0]
DDRDM[1] corresponds to DDRDATA[15:8]
DDRDM[2] corresponds to DDRDATA[23:16]
DDRDM[3] corresponds to DDRDATA[31:24]
DDRDM[4] corresponds to DDRDATA[39:32]
DDRDM[5] corresponds to DDRDATA[47:40]
DDRDM[6] corresponds to DDRDATA[55:48]
DDRDM[7] corresponds to DDRDATA[54:56]
(Refer to the DDR Data Bus Multiplexing section in Chapter 7 of the RC32438
User Reference Manual.)
I/O DDR Data Strobes. DDR byte data strobes used to clock data between DDR
devices and the RC32438. These strobes are inputs during DDR reads and out-
puts during DDR writes.
DDRDQS[0] corresponds to DDRDATA[7:0].
DDRDQS[1] corresponds to DDRDATA[15:8].
DDRDQS[2] corresponds to DDRDATA[23:16].
DDRDQS[3] corresponds to DDRDATA[31:24].
O DDR Bus Switch Output Enables. These pins are used to enable external
data bus switches in systems that support data bus multiplexing.
O DDR Row Address Strobe. The DDR row address strobe is asserted during
DDR transactions.
Table 1 Pin Description (Part 2 of 9)
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May 25, 2004
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