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PDF C8051F230 Data sheet ( Hoja de datos )
| Número de pieza | C8051F230 | |
| Descripción | 48-Pin MCU | |
| Fabricantes | ETC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de C8051F230 (archivo pdf) en la parte inferior de esta página. Total 2 Páginas | ||
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C8051F230
ANALOG PERIPHERALS
Two Comparators
- Programmable Hysteresis
- Configurable to Generate Interrupts or Reset
VDD Monitor and Brown-out Detector
ON-CHIP JTAG DEBUG
- On-Chip Debug Circuitry Facilitates Full Speed,
Non-Intrusive In-System Debug (No Emulator
Required!)
- Provides Breakpoints, Single Stepping,
Watchpoints, Stack Monitor
- Inspect/Modify Memory and Registers
www.DataShe-et4U.Scoumperior Performance to Emulation Systems Using
ICE-Chips, Target Pods, and Sockets
- Low Cost, Complete Development Kit
SUPPLY VOLTAGE ......................2.7V to 3.6V
- Typical Operating Current: 9mA @ 25MHz
- Typical Stop Mode Current: <0.1uA
Temperature Range: –40°C to +85°C
48-Pin TQFP Package
8K Flash, 256 RAM, 48-Pin MCU
PRELIMINARY
8051-COMPATIBLE µC Core
- Pipelined Instruction Architecture; Executes 70%
of Instructions in 1 or 2 System Clocks
- Up to 25MIPS Throughput with 25MHz Clock
- Expanded Interrupt Handler
MEMORY
- 256 Bytes Data RAM
- 8k Bytes FLASH; In-System Programmable in 512
byte Sectors
DIGITAL PERIPHERALS
- 32 Port I/O (All 5V tolerant with High Sink Current)
- Hardware SPITM and UART Serial Ports Available
Concurrently
- Three General Purpose 16-bit Counter/Timers
- Dedicated Watch-Dog Timer; Bi-directional Reset
CLOCK SOURCES
- Internal Programmable Oscillator (2 to 16MHz)
- External Oscillator: Crystal, RC, C, or Clock
- Can Switch Between Clock Sources on-the-fly;
Useful in Power Saving Modes
SPI is a trademark of Motorola, Inc.
VDD
VDD
GND
GND
NC
NC
NC
NC
TCK
TMS
TDI
TDO
/RST
MONEN
XTAL1
XTAL2
Analog/Digital
Power
JTAG
Logic
VDD
Monitor
External
Oscillator
Circuit
Internal
Oscillator
Debug HW
8
0
5Reset
1
WDT
System Clock
C
o
r
e
8kbyte
FLASH
256 byte
RAM
SFR Bus
Port 0
Latch
UART
P
0
Timer 0
Timer 1
Timer 2
M
U
X
Port 1
Latch
CP0 CP0
CP1 CP1
CP0+
P
1
CP0-
CP1+
CP1-
M
U
X
SYSCLK
Port 2
Latch
SPI
P
2
M
U
X
Port 3
Latch
P P0.0/TX
0
P0.1/RX
P0.2//INT0
P0.3//INT1
D P0.4/T0
r P0.5/T1
v
P0.6/T2
P0.7/T2EX
P P1.0/CP0+
1
P1.1/CP0-
P1.2/CP0
P1.3/CP1+
D P1.4/CP1-
r P1.5/CP1
v
P1.6/SYSCLK
P1.7
P P2.0/SCK
2
P2.1/MISO
P2.2/MOSI
P2.3/NSS
D P2.4
r P2.5
v
P2.6
P2.7
P P3.0
3
P3.1
P3.2
P3.3
D P3.4
r P3.5
v
P3.6
P3.7
7.15.2002
1 page | ||
| Páginas | Total 2 Páginas | |
| PDF Descargar | [ Datasheet C8051F230.PDF ] | |
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