PDF AKD4122 Data sheet ( Hoja de datos )

Número de pieza	AKD4122
Descripción	24-Bit 96kHz SRC
Fabricantes	Asahi Kasei
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Hay una vista previa y un enlace de descarga de AKD4122 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas
No Preview Available ! ASAHI KASEI [AK4122] AK4122 24-Bit 96kHz SRC with DIR GENERAL DESCRIPTION The AK4122 is a digital sample rate converter (SRC) with the digital audio receiver (DIR). The input sample rate ranges from 8kHz to 96kHz. The output sample rate is 32kHz, 44.1kHz, 48kHz or 96kHz. By using the AK4122, the system can take very simple configuration because the AK4122 has an internal PLL and does not need any master clock at slave mode. Then the AK4122 is suitable for the application interfacing to different sample rates like Car Audio, DVD recorder, etc. www.DataSheet4U.com FEATURES 1. SRC • Asynchronous Sample Rate Converter • Input Sample Rate Range (fsi) : 8kHz ∼ 96kHz • Output Sample Rate (fso) : 32kHz, 44.1kHz, 48kHz, 96kHz • Input to Output Sample Rate Ratio : 0.33 to 6 • THD+N : −113dB • I/F format : MSB justified, LSB justified (16/24bit) and I2S compatible • Clock for Master mode : 256/384/512/768fs • SRC Bypass mode • Soft Mute Function 2. DIR • 4-Channel Inputs Selector & 1-Channel Through Output • AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible • Low Jitter Analog PLL • PLL Lock Range : 32kHz ∼ 96kHz • Auto detection - Non-PCM Bit Stream - DTS-CD Bit Stream - Validity Flag - Sampling Frequency (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz) - Unlock & Parity Error - DAT Start ID • 40-bit Channel Status Buffer • Burst Preamble bit Pc, Pd Buffer for Non-PCM bit streams • Q-subcode Buffer for CD bit streams 3. 4-wire Serial µP Interface 4. Power Supply • AVDD: 3.0 ∼ 3.6V (typ. 3.3V) • DVDD: 3.0 ∼ 3.6V (typ. 3.3V) 5. Ta = −10 ∼ 70°C 6. Package : 48pin LQFP MS0267-E-03 -1- 2004/08 1 page ASAHI KASEI [AK4122] 25 R 26 AVSS 27 PDN 28 29 30 31 32 www.DataSheet4U.com 33 34 35 36 37 38 39 40 41 42 43 44 45 LRCK1 BICK1 SDTI DVSS DVDD MCLK2 LRCK2 BICK2 SDTIO INT0 INT1 TX SDTO BICK LRCK OMCLK DVSS DVDD 46 BVSS 47 CSN 48 CCLK External Resistor Pin - 12kΩ±5% resistor should be connected to AVSS externally. - Analog Ground Pin Power-Down Mode Pin I “H”: Power up, “L”: Power down reset and initializes the control register. I Input Channel Clock Pin I Audio Serial Data Clock Pin I Audio Serial Data Input Pin - Digital Ground Pin - Digital Power Supply Pin, 3.0 ∼ 3.6V I Master Clock Input Pin I/O Input / Output Channel Clock Pin I/O Audio Serial Data Clock Pin I/O Audio Serial Data Input / Output Pin O Interrupt 0 Pin O Interrupt 1 Pin O Transmitter Output Pin O Audio Serial Data Output Pin I/O Audio Serial Data Clock Pin I/O Output Channel Clock Pin I Master Clock Input Pin - Digital Ground Pin - Digital Power Supply Pin, 3.0 ∼ 3.6V Substrate Ground Pin - This pin should be connected to AVSS. I Chip Select Pin I Control Data Clock Pin Note: All input pins except internal biased pins should not be left floating. MS0267-E-03 -5- 2004/08 5 Page ASAHI KASEI Parameter Output for PORT3 (Slave mode) BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “↑” (Note 11) BICK “↑” to LRCK Edge (Note 11) LRCK to SDTO (MSB) (Except I2S mode) BICK “↓” to SDTO Output for PORT2 (Master mode) BICK2 Frequency www.DataSheet4U.com BICK2 Duty BICK2 “↓” to LRCK2 BICK2 “↓” to SDTIO Output for PORT3 (Master mode) BICK Frequency BICK Duty BICK “↓” to LRCK BICK “↓” to SDTO Control Interface Timing CCLK Period (Note 12) CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CSN “↓” to CCLK “↑” CCLK “↑” to CSN “↑” CDTO Delay CSN “↑” to CDTO Hi-Z Reset Timing PDN Pulse Width (Note 13) Symbol tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD fBCK dBCK tMBLR tBSD fBCK dBCK tMBLR tBSD tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tDCD tCCZ tPD min 1/64fs 65 65 30 30 −20 −20 −20 −20 200 80 80 40 40 150 50 50 150 typ 64fs 50 64fs 50 Note 11. BICK rising edge must not occur at the same time as LRCK edge. Note 12. In case of using INT2. When INT2 is not used, the max value is not limited. Note 13. The AK4122 can be reset by bringing the PDN pin = “L”. [AK4122] max 30 30 20 30 20 30 1000 45 70 Units ns ns ns ns ns ns ns Hz % ns ns Hz % ns ns ns ns ns ns ns ns ns ns ns ns ns MS0267-E-03 - 11 - 2004/08 11 Page

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